Design And Implementation Of 10 Gigabit Ethernet Controller

With the rapid development of network information technology,the demand for massive information transmission is growing,and traditional communication interfaces have been difficult to adapt to various applications of high bandwidth.10 Gigabit Ethernet has a high transmission rate,a wide range of application scenarios,low cost.Therefore,the application of 10 gigabit Ethernet will be more and more widely,and it is of significance to complete the design of 10 gigabit Ethernet Media Access Control(MAC).This paper is designed for Multi-core Digital Signal Processor(DSP)to design a 10 Gigabit Ethernet MAC layer controller that meets the IEEE 802.3ae protocol.Firstly,research the hierarchical model in the IEEE 802.3ae protocol,and analyzed in detail on the Ethernet frame format,Media Independent Interface(XGMII),Ethernet flow control method,cyclic redundancy check and deficit idle counting algorithm.Secondly by the above theoretical research and the corresponding multi-core DSP system to high-speed peripheral interface requirements,the overall framework and module division of the MAC control system are determined.According to the corresponding module function,the top-down design principle is used,and the overall design of the MAC controller is completed based on the Verilog hardware description language.In the design process,sub-modules are described in various ways,such as structure diagrams,flow charts and state machines to complete the design work.In addition,in order to implement verification of the MAC layer controller,the modular level and system-level verification environment are built.At the same time,in order to shorten the verification cycle,the product is put into production,and the logic synthesis of FPGA is used,and the maximum operating frequency after the integrated is 354.23 MHz.The simulation waveform is detected by a logic analyzer to ensure that the MAC controller can achieve the expected function on the hardware circuit.Finally,based on the verification principle of coverage drive,the collection of Cadence's IMC software completes the code coverage,and the code coverage can reach more than 90% after performing multiple regression tests.The Design Compiler tool is used to complete the logic synthesis under the28 nm process library.According to the timing report,the MAC controller can operate at312.5 MHz frequency and can reach the throughput rate of 10 Gbps.Based on the above front-end design and FPGA verification,the 10 Gigabit Ethernet controller designed to meet the IEEE 802.3ae standard.This paper is of great significance for further improving network bandwidth and promoting 10 Gigabit Ethernet applications.