Design And Implementation Of Hardware Circuit To Defend Against Row Hammer Attack

With the continuous development of memory technology,a number of memory cells per unit area of a chip have gradually increased and the space between them has become narrow as well.The memory cell coupling caused by repeated switching of DRAM word lines has led to an attack pattern of data flips--Row Hammer attack,which would break people's recognition on the high reliability of memory devices,trigger an information security crisis,and pose a huge threat to the mainstream system architecture on the market.There are two ways to achieve defense against Row Hammer attacks:software and hardware.However,most of the current defense solutions implemented by software are limited by the software environment or have shortcomings such as attack vulnerabilities,making the final defense effect unsatisfactory.Since this attack is achieved by exploiting the hardware defects of DRAM memory architecture,the current defense method implemented by hardware has the disadvantages of large power consumption and large area,thus the design and implementation of hardware defense circuit with smaller area and lower power consumption has become the mainstream of research.The subject originates from a corporate project and it aims to carried out the hardware design and research work applied to DDR chip defense against Row Hammer attacks.The main content of the research is as follows:(1)Through the analysis and research of Row Hammer attack and DDR workflow,this paper adopts the method of counting the number of activations of different rows of addresses to design and implement an attack detection module that detects whether the current DDR is being attacked by Row Hammer.Based on the minimum delay required for normal read and write access of DDR,the module uses the bypass circuit to monitor address signals in parallel,selects frequently activated row addresses and counts the number of activations,so as to obtain the result of detecting Row Hammer attacks in the refresh cycle.(2)Based on the analysis of the AXI4 bus protocol,this paper proposes a delayed activation hardware defense method.This method obtains the mapping relationship between the AXI address and the DDR physical address by studying the internal address translation algorithm of the DDR controller,and delays the transmission of the AXI address signal containing the activation command according to the output result of the attack detection module,so as to reduce the number of activations of the rows of addresses in the refresh cycle to realize the defense against Row Hammer attacks.(3)For the designed Row Hammer attack defense circuit,this paper uses the VCS simulation tool to complete the dynamic simulation of each functional module,and use Xilinx Vivado software to complete the circuit compilation and download it to the VC709development board.The board level verification uses UART 16550 to connect and read the data in the addresses.The verification results show that the attacker can only achieve 107k Row Hammer attacks by applying the defense scheme within the 64ms refresh period,which is far lower than the minimum number of attacks required to generate disturbance errors.The success rate of Row Hammer attack is reduced by at least 23%,reaching the expected design goal.In this paper,the TSMC tt28nm process library is used to logically synthesize the entire defense scheme,and the overall structure area is 0.14mm~2,and the power consumption is 24.25m W.Compared with the original DDR chip,the area cost of the DDR chip with the added attack defense circuit has increased by 4.5%,and the power consumption has increased by 2.9%.The defense against Row Hammer attack circuit designed in this paper includes attack detection and attack defense modules,which can provide relevant technical references for the design and research of defense against Row Hammer attacks.