Research On Plasma Etching And Key Technology Of GaN HEMT

Gallium nitride?GaN?is one of the third generation of wide bandgap semiconductor materials developed rapidly in the past ten years.AlGaN/GaN high electron mobility transistor?HEMT?has the excellent characteristics such as high transconductance,high saturation current and high cutoff frequency.Plasma dry etching is a common technique for GaN HEMT manufacturing,and has been very important in key processes such as mesa isolation etching,ohmic region and recessed-gate etching.Due to the plasma etching is very important and very flexible,the scientific researchers usually use plasma etching to achieve different needs.In this paper,on the basis of the key technology of plasma etching and GaN HEMT background,we set up the following two experiments:1.The research of ohm region plasma etching structures 2.the research of recessed-gate plasma etching and oxidation structures.The effects of plasma treatment on the structure,surface morphology and electrical properties of the device are studied in different aspects.In the experiment,different etching times and diameters were set:0.8?m?small hole?,1.6?m?middle hole?,and 3?m?large hole?.The etching area duty is 15%,30%and 45%respectively.The results show that the patterned etching structure can obtain a lower contact resistance,on the one hand,the ohmic region etching will remove the irregular surface oxide and pollutants.On the other hand,the patterned etching will result in a large number of sidewall areas,which undergo an annealing and Ti reaction to form TiN,resulting in more N vacancies.At the same time,the thickness of the AlGaN of patterned etch structure has an edge effect,which leads to the increase of the 2DEG concentration.The 20s patterned etching obtained the ohmic contact resistance of 0.18?·mm,and three kinds of aperture for the contact resistance had no significant effect.In addition,metal surface morphology structure of the patterned etching and whole etching has excellent structure,the RMS of the whole etching structure is 19.84 nm,only half of the traditional structure of RMS,which indicates that due to the increase in the ohmic region below the barrier layer etching process,effectively eliminate the deep nail,inhibit the high electric field ohm contact below the production,so as to avoid the strong electron injection.The breakdown voltage of the conventional structures,the patterned etching structures and whole etching structures were 124V,147V,191V.With the increase of etching process,the breakdown voltage of all etching and etching structures is improved significantly.Subsequently,in order to obtain a more precise hole,an attempt was made to use PECVD to deposit the Si N thin layer,and to be used as a mask.The second experiment of plasma etching and GaN in this paper,combined with the F-ion barrier structure,recessed-gate structure,MIS HEMT enhanced devices as the background,based on the recessed-gate structure,adding a step of O₂ plasma treatment.The effect of recessed-gate structure with plasma oxidation process on the device characteristics were studied.The experiment set up six different devices,respectively:conventional devices,conventional with oxidation device,shallow recessed-gate structure,shallow recessed-gate with oxidation device,deep recessed-gate structure and deep recessed-gate with oxidation device.Through the test and analysis,found that the recessed-gate with oxidation device can be integrated advantages of recessed-gate and the MIS structure,the threshold voltage is floating to 0.4V,producing enhanced device.The transconductance is large and the leakage current is small,but the saturation current decreases.In the CV characteristics of the test,it was found that the oxidation of the structure at different frequencies to get the approximate opening voltage,and the oxidation of the opening voltage with the frequency of the changes produced a significant difference.It is shown that the interface states are introduced after the oxygen plasma treatment,and the gate capacitance is affected by the interface state trap.