Design Of DME Airborne Receiver Based On FPGA

The DME navigation system is a land-based radio navigation system,which is a near-range navigation system based on the measurement principle of the secondary radar system.The whole DME system is mainly divided into the ground beacon platform and the airborne rangefinder,and the airborne part is responsible for asking the ground station for answering.The main research object of this paper is the receiver part of the airborne equipment of the DME system.Main main work is as follows:1.Because the active airborne DME receiver is mainly analog circuit,and the use proportion of integrated circuit is small,so the circuit system is relatively complex,high debugging difficulty and high maintenance cost.Based on the deep analysis of the signal processing process of DME airborne receiver,the digital circuit design scheme with FPGA as the core,which promotes the development direction of miniaturization,low power consumption and low cost.2.Combined the signal characteristics and working principle of DME system,and divides the overall receiver system into two parts: analog front-end processing circuit and digital signal processing circuit.The task of analog front-end is mainly to downconvert the modulation signal received from the duplex antenna to the 70 MHz medium frequency suitable for digital processing through a series of processes such as amplification,filtering and hybrid processing.The performance indicators of the system noise coefficient,isolation of different channels and gain inconsistency will be controlled in this part.The digital signal processing circuit is mainly divided into digital receiving channel and baseband signal processing.The digital reception channel mainly includes a digital filter to package the sampled modulation signal with a digital filter,processing the resulting bell pulse baseband signal as a binary rectangular pulse signal,and using the rectangular pulse as an interrupt trigger signal of DSP.The main completion of the baseband signal processing module matches the station address code and Moss decoding of the ground station;by alternately switching the search mode and tracking mode in DSP,searches and locks the distance code trigger pulse generated by the digital receiving channel,thus continuously provides relevant derivative data such as distance,proximity speed and the arrival time for the pilot.3.This article is based on FPGA,Distance ranging and address code identification module is established using algorithm,Compared to the analog filter filtering in the conventional DME,Consumless hardware resources effectively saves the cost of the area of the circuit;The desk address decoding module for Moss code is also designed directly in FPGA,Different from the traditional method of converting the Moss encoding signal directly to the audio system into the tone signal output,This paper uses HDL description to code it in real-time and send it to the display unit via the bus system,It can more intuitively allow the pilot to get the station address code information of the ground platform currently interacting with the local computer.At the same time,DSP discusses how to conduct fast search from many answer signals,lock the answer pulse signal belonging locally and continuously track it.Compared with the traditional way of screening the judgment one by one,the fast search algorithm proposed herein has a faster locking speed and a shorter inlock recapture time.4.Finally debugging the whole system,and the test results show that the function and performance of the receiver module designed in this paper meet the design requirements.Application flexibility,lower production and maintenance costs,and lower power consumption,and lay the foundation for subsequent functional upgrades and miniaturization,but also improve distance measurement accuracy and reliability.In conclusion,the main innovation points of the DME airborne receiver designed in this paper are: the design scheme of FPGA + DSP greatly reduces the volume,power consumption and cost of the system.Effectively improve the ranging accuracy,reliability and debugging of the equipment;in FPGA,special address code and ranging code identification module is designed and directly connected,effectively improving the ground information processing speed;the improved fast search algorithm has shorter search locking time and unlocked recapture time.