Design And Implementation Of Dynamic Bit Width Adjustment Technology In Artificial Intelligence Processor

In recent years,deep learning has become the most advanced and widely used core technology in the field of artificial intelligence,and is widely used in fields such as natural language processing,image recognition,and assisted driving.However,most of the artificial intelligence processing represented by deep neural networks are computing-intensive and storage-intensive tasks,which makes it difficult to deploy increasingly complex depths on end-side devices such as the Internet of Things and embedded computing resources with limited computing resources.Learning algorithms and the extremely demanding requirements for power consumption make traditional computing platforms face more and more difficulties.In order to break through the bottleneck of traditional chip architecture in terms of computing power and energy consumption,dedicated artificial intelligence processors rely on its innovative computing architecture to efficiently accelerate neural network computing and greatly reduce power consumption.It has become a research hotspot in academia and industry.However,there is still the problem of fixed bit width,which can't be applied to various devices with limited computing resources.One is insufficient computing power,and the other is small storage space.Based on the existing artificial intelligence processor of the project,the paper proposes a dynamic bit width adjustment technology with software and hardware cooperative work by mining the data characteristics in the neural network application,which reduces the high-bit-width floating-point data to low-bit-width fixed-point data in the quantization software and designs a parallel computing circuit for low-bit-width fixed-point data in hardware implementation.This method reduces the required data bit width from the source,improves the computing power,reduces the power consumption caused by frequent memory access,and makes the finally realized processor have a higher energy efficiency ratio.The main results of the paper are as follows:(1)Using linear quantization method,the paper designs a quantization software tool chain based on dynamic bit width adjustment technology.The paper uses Python as the software development environment,starting from linear quantization expressions,quantizing FP32to INT8,and the data bit width is reduced by 75%during the conversion process.The paper selects Keras as the neural network programming framework.After Alex Net network training,the HDF5 network model is obtained.At the same time,the input image data is converted to extract the quantitative parameters,and then the instructions,weights,and data files are generated.The tools are converted into the data format supported by the chip.Three files are prepared for chip verification test.(2)Using the state machine design method,the paper conducts hardware design research based on dynamic bit width adjustment technology.The paper uses a set of efficient PE circuit architecture design to simultaneously support basic operators of deep neural networks such as convolution,pooling,and full connection.The paper uses quantized parameters as the module port input,and the circuits of the PE hardware module are all designed for fixed-point parallel calculation.Compared with the use of floating-point hardware design,the design area and complexity of the paper are greatly reduced.The paper uses Model Sim software to verify the simulation function,and successfully loads and calculates the instructions,weights,and data files,completing the forward derivation process of the deep neural network.(3)Using Opal Kelly XEM7350 development board,the paper conducted FPGA prototype verification of the overall circuit design.The paper writes an FPGA development environment based on Python language,completes the design synthesis on Vivado software,and generates a bitstream file for placement and routing.After running the Python program,the bitstream file is automatically loaded.This file carries out resource configuration and design mapping for FPGA.Based on instructions,weights,and data files,the paper deploys the Alex Net network on Xilinx Kintex7 FPGA,and compares the FPGA calculation results with the Python calculation results.The average error is within 3%,which proves that the reduction of the data bit width will not affect the accuracy of the calculation results and verify the correctness of the dynamic bit width adjustment technology.(4)The artificial intelligence processor based on the design ideas of the paper adopts all-digital circuit design and implementation,which solves the key problem that the fixed data bit width of the traditional architecture is not applicable to devices with limited computing resources,and realizes an innovative method that the data bit width can be dynamically adjusted.The main results obtained in the paper are that it can support the deployment of deep neural networks such as Alex Net,have a complete software development tool chain,and be compatible with the Keras deep learning framework.After circuit synthesis,the hardware design has an area of 7.96mm~2,a main frequency of260MHz,and a low power consumption of 267m W.