Design Of Recurrent Neural Network Module For Embedded AI Processor

At present,artificial intelligence technology has made breakthrough progress in various fields such as scientific research,medical treatment,finance,education,transportation,etc.,and has become the core development direction of the current scientific research industry and industry.At the same time,chips are used as various electronic devices everywhere.With the core components,designing a multifunctional chip based on artificial intelligence is also the trend.However,the current existing artificial intelligence chips are difficult to deploy in scenarios where energy consumption is demanding,such as the Internet of Things,automotive,navigation,etc.,due to the low internal power of the chip,which is several watts and tens of watts,and low-power chips cannot run complex algorithm,making its use very limited.In order to break through the bottleneck of traditional chip architecture on deep learning technology in computing power and energy consumption,ASICs rely on its powerful computing capabilities,advanced manufacturing technologies,and processor architectures that are completely different from CPU and GPU.The calculation has been greatly accelerated and the power consumption has been effectively reduced.The chip team of the internship unit proposes a deep learning neural network artificial intelligence processor design based on the reconfigurable array architecture.This project aims to expand the programmable ability of the existing processor,and realize the real-time and efficient part of the long short-term memory network(LSTM)of the circulating network through the customized design of instruction set,neuron computing unit,input-output system and storage system Department.The design of the short and long term memory neural network module can expand the application of intelligent chip in edge computing.In order to realize the network module,the software MATLAB is used for modeling and performance analysis in this project.The Py Torch framework realizes network construction and network training inference,so as to obtain the data and weight parameters in the training completed network for quantitative processing,which is used to support the subsequent FPGA verification and test work.At the same time,the special state machine of LSTM is designed and built according to the algorithm of LSTM network,and the network is deployed to the whole chip network.In this project,a design of data flow processor based on reconfigurable configuration is proposed.The processor adjusts the control mode of data flow according to different neural network cores to allocate different functional modules and on-chip and off chip storage units.In addition,a long short-term memory neural network architecture,which combines 16 neuron computing units with control core,is proposed.When only RAM storage is configured on the chip,the power consumption is reduced by three orders of magnitude compared with GPU,only about 30 m W to 50 m W.In the project,Modelsim is used as the simulation tool,Vivado is used as the development platform,and top-down design idea and modular design method are adopted.In order to enable the chip to support high-speed algorithm and be able to process large data sets of neural network,DDR IP core is designed and built to complete the logic integrated layout and wiring,and only about 1W on-chip power consumption is obtained.Based on the training network data and configuration chain parameters,the hardware circuit is verified and analyzed by using kinetex-7 series xem7350 development board.The design module of this project realizes the incorporation of long-and short-term memory neural network modules into the design of reconfigurable chips.and the 4-division multiplexing method is proposed to effectively improve the utilization rate of neuron computing unit,improve the computing efficiency and reduce the power consumption.Using on-chip and off-chip storage to enhance storage flexibility,and researching and publishing papers related to reconfigurable data flow processor patents to support multiple neural networks for module reconfigurable configuration,to achieve the goal of data flow reconfigurable.