Design Of Binary Neural Network Memristive Accelerator

In recent years,with the development of deep learning and computer theory,artificial intelligence(AI)has gradually highlighted its powerful functions in various fields.With the rise of the concept of in-memory computing,the bottleneck of traditional von Neumann computer architecture is expected to be solved,and more importantly,the emerging nonvolatile memory devices represented by memristors pushes AI from the cloud computing to the user's edge computing,but also puts higher requirements on hardware implementation.Binary neural networks have received a lot of attention because of their small storage space,fast computing speed and low energy consumption,which are well suited for edge AI applications.In this paper,we address the shortcomings in the traditional binary neural network memristor accelerators,conduct research and propose corresponding methods and considerations on key issues such as weight hardware implementation,robustness,and batch normalization hardware implementation.Our works provide original innovations and theoretical basis for future computer architecture that computing and memory will converge.The relevant research work is as follows:(1)In the study of weight hardware implementation,this work proposes a select column architecture for the shortcomings of traditional differential pair architecture by adjusting the binary neural network to a hardware-friendly network with activation value 0/1 and weight value+1/-1 and combining the characteristics of the binary neural network function.With its small area and simple circuitry,the select column architecture passes the MNIST handwriting recognition task validation.(2)In the study of robustness,this paper uses laboratory-fabricated W/Al O_x/Al₂O₃/Pt binary memristors as binary weight units,performs binary neural network simulation based on their measured electrical characteristics.We build error model and evaluates the robustness of the proposed select column scheme.The results show that the binary neural network memristor accelerator select column scheme is able to achieve the expected network accuracy with different non-ideal factors such as device variation,device on/off ratio,device yield,device and circuit noise,and has a high robustness with non-ideal factors.(3)In the study of hardware implementation of batch normalization,the purposed memristive K-constant batch normalization method combines the binary neural network batch normalization operation and activation function into a single step operation and implemented in the memristor array.The new method significantly reduces the peripheral circuit complexity and maintains the network flexibility.The network simulation shows that the memristive K-constant batch normalization method has better network accuracy than the high-precision CMOS batch normalization method with the device variation less than 0.5,and ideally achieves 96.1%network recognition rate.