Evaluating RISC-V Vector ISA Extension With Computer Vision Workloads

Computer vision(CV)algorithms have been extensively used for a myriad of applications nowadays.With the rapid development of Internet of Things(IOT),multimedia applications such as CV algorithms in embedded systems need more efficient processing to meet the real-time requirements.As the multimedia data(such as images and videos)are generally well-formatted and regular,it is beneficial to use Single Instruction Multiple Data(SIMD)instructions to improve the performances of CV algorithms.SIMD instructions are capable of conducting the same operation on multiple data items in a single instruction,are extensively employed to improve the efficiency of CV algorithms.However,SIMD instructions in X86 and ARM architecture have some limitations,such as the fixed length of instruction,limited parallelism,the problem with processing the edge data,and the poor hardware compatibility.RISC-V Vector extension instruction separates opcode and the length of data sets,and has the characteristics of variable vector length and register combination,which can provide higher flexibility and portability.However,the effectiveness and performance of RISC-V vector instruction for CV algorithm are unknown.With a set of inline assembly functions implemented,the typical CV algorithms,such as gray level,mean filter,and edge detection are transplanted in RISC-V and evaluated for their effectiveness and performance.The result shows that compared with the baseline Open CV implementation that uses scalar instructions,on average to accomplish the same task,a CV algorithm needs about3 x fewer instructions when it is implemented with version 0.8 RV-V instructions.Moreover,by grouping 8 vector registers to form long registers during processing,the algorithm can be implemented with an additional 8x reduction in the number of committed instructions(totally about 24 x reduction).The experiment verifies the design characteristics of RISC-V vector instruction and proves the potential of RISC-V vector instruction in CV algorithm.