Design Of Lightweight Cryptographic Algorithm Circuit Based On MTJ/CMOS Memory Internal Logic Structure

With the rapid expansion of electronic information technology and semiconductor IC industry,the more convenient and intelligent lifestyle is offered by Io T technique.The enormous information is increasingly transmitted between not only human and smart devices but also among devices.Lightweight encrypting algorithms are now widely applied in Io T devices because of their comparatively low resource budget in encryption.However,the security of Io T information is seriously threaten by rapid growth of diverse power attacks at present.In this case,it will benefit the development of Io T security industry a lot by researching the encrypting algorithms with low power consumption and excellent protecting capability.The sharply focused Magnetic Tunnel Junction(MTJ)which is of nonvolatility and low power budget is proposed in this paper for the application in the design of encryption circuits based on lightweight algorithms by analyzing the international research achievement.According to the architecture of conventional Sense Amplifier Based Logic(SABL)and the advantages of MTJ devices,the structure of anti-attack MTJ/CMOS in-memory new logic elements is proposed in the article.The model of circuit elements is successfully built based on Cadence environment with SMIC40 nm CMOS process and MTJ Verilog-A model.The complete circuit models in both typical lightweight encrypting algorithms of PRESENT-80 and Piccolo-80 are simultaneously constructed in the condition of using original algorithm circuits.The validity of two models is apparently proved by hybrid simulation.In order to estimate the security and overall performance of newly structured circuits,a completely automated platform for power consumption collection is designed for circuits model of encryption algorithm in Cadence to directly collect vast power consumption data in analog encrypting process.Correlation Power Analysis(CPA)is arranged to hack secret key in encryption by utilizing obtained data.In the meanwhile,the analysis of power consumption and circuits area occupation is also implemented.According to the final results of experiment and research,the relativity between power consumption and data in encrypting is obviously eliminated for resisting power attach by applying proposed MTJ/CMOS in-memory logic elements.MTJ/CMOS in-memory logic elements present much better advantages of power consumption for the identical level protection and the inconspicuous disadvantages of area occupation comparing with conventional circuits level protecting elements.All of the results indicate that there are tremendous benefits in MTJ/CMOS inmemory logic elements for the design of hardware encryption circuits.