Dynamic Switching Of Memory Access Focus In Data Permeation And Migration On Processor Chip

Computer performance is restricted by the "storage wall",an important factors to improve processor requests in the cache hit ratio is an important way to solve the problem of storage wall,fade out Moore's law efficacy of hardware conditions,the optimal structure can provide a good environment for the processor's cache is a breakthrough to improve's shooting.Based on processor locality principle,in the form of similar to water permeation will just-in-time locality group(a group of address on the space adjacent blocks of data)in the spring,drawing on the cache as a basic component of osmosis migration flows in the cache configuration,make data with active attitude to cater to the processor's requirements,will need to access the data processor permeation in the cache"spring".Specifically,when the processor requests to access the data in a data block,the data block,together with its surrounding data blocks,will form a just-in-time licality group,and the whole group as a unit to migrate to the chip cache permeation is a feasible concrete way.In previous work,just-in-time locality group in the choice of "around the block" is the focus of the current processor request access data block as the center,around the neighborhood for the seepage data block is called together,this way the compromise choice not in real time with the right attitude to adapt to application in irregular access to the execution of the processor.In this paper,statistics are carried out according to the changes of processor access behavior,and dynamic changes of statistical results are used to guide the dynamic changes of neighborhood of just-in-time locality group.In this way,permeation data migration can be carried out in a way that is more consistent with the current processor access intention,and a good access environment can be created for the processor.The algorithm of cold and hot permeation data allocation and a preliminary circuit design idea are proposed.In addition,this paper preliminarily proposes a performance evaluation model suitable for the above mentioned permeation cache structure,including access memory cost and data flow cost.Access memory cost mainly to access memory time as main index,access memory time estimation is based on the analysis of the processor's access process,it's time is divided into multiple stages,in order to estimate the permeation cache each stage access time scope,it is concluded that in a certain access mode,in the draw cache hit is superior to the traditional cache hit at the same level of conclusions;data flow cost is to analyze the difference between traditional cache and penetrating cache data flow mode,and to include the number of data blocks that need to be migrated and the number of data blocks that need not be migrated after the processor's request for data blocks in the just-in-time locality group hit into the evaluation standard of data flow cost.Finally,the Verilog hardware description language and Model Sim experimental platform are used to carry out simulation experiments.By simulating the load/store instruction execution and data flow between storage levels of the processor,it is proved that the dynamic neighborhood permeation has certain advantages over the symmetric neighborhood permeation in cache hit rate,data flow and other aspects.