Face Recognition Based On Improved Convolutional Neural Network Algorithm And Its FPGA Implementation

With the development of network and computer vision,various media and applications appear in people's lives,and the consequent network and information security issues have received widespread attention.With the non-invasive characteristics of face recognition technology,it has become one of the most concerned technologies in the field of artificial intelligence.It is of great importance in practical applications,such as video surveillance,human-computer interaction,security system and so on.The current frontal face recognition technology has reached a high level of accuracy,but when the people's face are partially covered,the accuracy of algorithm recognition needs to be improved,and the model is largely relative.In response to these problems,this paper improves a face recognition algorithm based on FaceNet,and carries out FPGA design and implementation.This paper's main contents are as follows:First,a face recognition algorithm based on FaceNet is improved.Use MTCNN for target detection,improve the lightweight network SqueezeNet,and use it to replace Inception-ResNet-V1 for feature extraction.The triplet is used for training,and the same number of partially occluded images are added to the Asian face training data set CASIA-Face V5 to improve the accuracy of the model.The recognition is completed by comparing the Euclidean distance between different images.The experimental results show that the improved face recognition algorithm has a certain improvement in recognition accuracy.Secondly,FPGA is used to design the algorithm.We analyze and study the possible parallelism of the algorithm,and evaluate the calculation process of the improved face recognition algorithm and the multiplication of each layer.Then the FPGA design of the convolutional layer,the pooling layer and the overall system architecture was carried out,and the optimization design method of hierarchical pipeline was proposed to reduce the communication bandwidth.Finally,the face recognition algorithm is implemented on FPGA.Use the development tools of Xilinx to implem ent hardware and software implement.Add the appropriate compilation instructions to the HLS code,and then expand the loop,optimize the calculation process of each input and output channel in the calculation of each layer of the convolutional layer,and use the dataflow instruction in the Vivado HLS tool to transfer the data and the processing is implemented in parallel.The experimental results show that the design of this paper shortens the computing time greatly when implementing the FPGA,and the computing performance has also been greatly improved.