Research On High Data Rate RFID Tag Design In CMOS Technology

Radio Frequency IDentification(RFID)is a ubiquitous technology nowadays with numerous applications benefitting human lives around the world.All these different types of applications have resulted in the need for research on diverse circuit architectures including high data rate RFID tag and reader circuits.Conventional passive Ultra high frequency(UHF)RFIDs operating in 900 MHz and 2.4 GHz bands work on passive backscattering technique.In this thesis,three low power high data rate amplitude shift keying(ASK)modulator circuits have been proposed for RFID tags operating in 10.5 GHz and 24 GHz bands.The modulators are based on voltage-controlled oscillators(VCOs)to generate their own carrier frequencies.In the first design,current reuse VCO has been used because of its lower power consumption and low phase noise compared to conventional cross-coupled VCO,to design a low power and high data rate ASK modulator which can be incorporated in a self-powered RFID tag.The modulator is designed in GF 130 nm CMOS technology and operates at 10.5 GHz central frequency.It consumes 864 μW from a dc supply of 1.2 V drawing an average current of 720μA.The modulator can communicate at a rate of 40 Mbps.Owing to the stacked series connection of the cross-coupled PMOS-NMOS pair,the current reuse VCO draws half the average current and much less power compared to the conventional cross-coupled NMOSNMOS or PMOS-PMOS VCO.The post-layout simulations of the 0.5 x 0.5 mm2 IC are carried out along with Corner and Monte Carlo simulations to predict the circuit behavior in worst case Process,Voltage and Temperature(PVT)variation scenarios.In the second design,adaptive body-biasing technique is used to realize a low power,low phase noise current reuse VCO and consequently an ASK modulator for RFID tag application.Deep N-well NMOS is used instead of the normal NMOS in the cross-coupled pair for the application of the body-biasing signal.This effectively isolates the common substrate and avoids the current path through it.The design uses the fact that if the bulk terminal of the NMOS is at a higher potential than its source terminal,the threshold voltage decreases and vice versa.This technique in addition to injection locking and current reuse mechanism reduces the power consumption of the modulator.The circuit consumes 790 μW with a 1.1 V voltage supply and oscillator phase noise at-106 dBc/Hz at 1 MHz offset.The modulator can produce 20 Mbps ASK signal.In the third design,a 24 GHz ISM band ultra-low power ASK modulatot is designed which employs an LC-biasing network with cross-coupled VCO.The biasing network achieves two goals;first it supplies the threshold voltage to the cross-coupled transistors irrespective of the supply voltage.This results in more control of the current flowing through the VCO circuit and achieves minimum power consumption.Second purpose is it acts as an impedance transformation circuit resulting in higher resonant frequency compared to conventional differential VCO designed with GF 130 nm CMOS technology PDK models.The ASK modulator’s IC layout measures 0.46 x 0.7 mm2.The post-layout results show power consumption of 490 μW with a 300 mV supply.All these designs propose a low power active circuitry solution for RFID modulator,which can rely on the energy harvested from the incoming electromagnetic signal.Different techniques have been incorporated in conventional and current reuse VCOs to achieve power efficiency.Modern challenges and opportunities for short range wireless communications demand new circuit solutions in different frequency bands with self-powered features for more usability.