The Design And Optimization Of A PVT Auto-tracking Cache Under Wide Supply Voltages

In order to reduce power consumption,modern processors often reduce the supply voltage when the light-weight workload is running.However,when the supply voltage scales down to near the threshold voltage of transistors,the performance of the static random-access memory(SRAM)will be seriously degraded due to the fluctuations of process,voltage,and temperature(Process Voltage Temperature,PVT).The degradation of the SRAM performance will affect the performace of the cache which consists of a large part of SRAM.Therefore,it is urgent to solve the problem of degradation of the SRAM performance at low supply voltage region.Applying the timing speculation technology to the cache design can improve the performance of cache under low voltage region.However,in previous works,the timing parameter of timing speculation SRAM is set by empirical methods without the guidance of theoretical analysis.To solve this problem,this paper proposes a performance model of timing speculation SRAM.With the guidance of the performance model,a PVT auto-tracking Cache module is designed,which can adaptively adjust the clock frequency of the system to achieve optimal performance.This PVT auto-tracking cache is implemented in the PULP SOC platform,and verified by RTL simulation.The PVT auto-tracking cache proposed in this paper and the cache in the PULP SOC are synthesized based on the TSMC 28 nm process library.Accoding to the analysis of the netlist,under the working conditions of 0.5V and 25°C,the PVT auto-tracking cache reduces the area by 88% compared to the PULP native cache,reduces the energy consumption of a single reference operation by 41%,and reduces the hit latency by 20%.