Research And Design Of A Single Photon Avalanche Diode Detector With High Speed And High Density

Single photon avalanche diode (SPAD) is becoming the most important active device of asingle photon detector due to many advatanges, such as large avalanche gain, fast response, highdetection efficiency, small volume and light weight, as well as its low power consumption.Within the ability to abtain the spatial and temporal information of a photon, integrated SPADarray detector is widely used in different fields of science to measure weak optical signals.Because reduction of the SPAD array area is now a limitation for the development of thistechnology, this thesis makes an in-depth study of the problem.First of all, a large size SPAD is traditionally used with the active area diameter from15μmto30μm. But in this paper, two new structures suiting for smaller size SPAD are proposed.Based on the deep N well process and STI process in SMIC0.13μm CMOS technology, thesimulation results and experimental results prove that the proposed small size SPAD can satisfythe requirements of a small dark count and low electrical field.Secondly, an EDA model for the SPAD is developed to improve the accuracy of mixedsimulation including the quenching circuit, the readout circuit and the SPAD. Verilog-A, ananalog hardware description language, is used to describe the model. The model characterizesthe current-voltage relationship under the Geiger mode. The after-pulsing, dark count andtemperature effect are also included in the model. Simulation results using Cadence SPECTREemulator agree well with the SPAD experimental results.Thirdly, a compact quenching and readout circuit with high response is designed. Transistorswith a lagre aspect ratio or resistances with a high value are frequently adopted to increase theresponse speed in the conventional design. In addition, a digital readout system is also usuallypresented to form a pixel unit, which costs large area for a high-speed counter and latch. In thisthesis, an active quenching circuit with only fve small transistors is proposed and reduces thedead time to6ns. Moreover, an anolog readout circuit based on the charging effect of capacitorsis designed to reduce pixel area and provide linear and logarithmic counts as same to.Finally, an array layout based on small-scale circuits is presented to make full use ofembedded spaces. With this scheme, the area of a4×4array is about200μm×220μm, and thespace utilization rate of a chip will reach up to82.98%.