Design Of Low Power Adaptive Loop Cache For IoT Applications

Battery-powered Internet of Things devices have high demands on the power consumption of internal microcontrollers(MCU).Cache can effectively reduce the number of CPU accesses to the main memory to improve performance and reduce power consumption.The existing Loop Cache structure can only cache the limited branches or sequentially executed instructions in the loop code.When the loop function instruction is called by a subfunction containing a large range of instruction jumps,the instruction in the cache needs to be Reload in main memory.Therefore,how to reduce the power consumption of the MCU system through the structure and circuit design of the Loop Cache has become a key issue to be solved urgently.The design of Loop Cache structure and memory circuit was studied in this thesis to improve cache hit ratio and reduce cache read and write power consumption.Based on the Core Mark benchmark program analysis of the Embedded Microprocessor Benchmark Consortium(EEMBC),an ASFLC(Adaptive Subfunction Loop Cache)structure that supports sub-function calls was proposed in this thesis.At the same time,in order to solve the problem of low read-write stability of low-power Loop Cache due to weak driving capacity at low voltage,a decoupled low-power storage unit DLP14T(Decoupling Low Power Bit Cell)suitable for ASFLC design was implemented circuit to further reduce the dynamic power consumption of ASFLC during operation.The ASFLC structure and memory cell based on the SMIC40 nm low-voltage process were designed in this thesis,and the core Mark test benchmark simulation has a hit rate of 62.38%,which is the same as the traditional dynamic circular cache(DLC))structure(40.03%)and adaptive circular cache(ALC))structure(41.01 %)In comparison,the hit rate increased by 22.35% and 21.37% respectively.The post-simulation results show that the decoupling memory cells with low voltage and high stability can perform stable read and write operations from 0.55 V to 0.75 V.The minimum power consumption is 0.55 V and the operating power is 245.5MHz.The read power consumption is 215.5n W.The area of the entire ASFLC is 1455.3 ?m2,accounting for about 3.7% of the entire MCU area.Comparing the CPU power consumption of the MCU system running Core Mark under the same Loop Cache capacity at the main frequency of 24 MHz,the ASFLC structure proposed in this thesis is reduced by 13.70% and 13.25% compared with the DLC and ALC structures,respectively.