Path Planning Algorithm For Hardware Designed

The path planning algorithm in navigation algorithm is always one of the core contents to be solved and optimized in the research of automatic navigation.With the rapid development of modern industrial technology and Internet,higher and higher performance are required for path planning search by people,such as timeliness,efficiency and accuracy.Nowadays,many algorithms implemented on CPU or GPU can not meet the requirements of people,so lots of algorithms are implemented into hardware,in order to improve the performance of the algorithms.synthesizing the algorithm into hardware can solve the problem of low efficiency of planning algorithm on industrial computer.At present,FPGA(Field programmable gate array)has strong portability,can repeatedly configure computing resources,and its internal logic can be changed according to requirements and so on.Many navigation algorithms used in embedded system are suitable for FPGA platform to realize hardware synthesis,finally achieve to accelerate algorithm.Using Verilog,VHDL and other hardware languages to develop and synthesize directly,we have to face the problems of long development cycle and difficult debugging results.In the case of loose performance requirements for the integrated hardware results and insensitive to potential risks,using high level synthesis(HLS)for development can greatly shorten the development cycle,save a lot of manpower,get good hardware results,and greatly improve the production efficiency.In this paper,I used the High Level Synthesis software Catapult of Mentor company,design and optimize the implementation of path planning algorithm in project.Then the improved algorithm can be successfully synthesized by software,got the corresponding parameters are ideal,and generate the corresponding RTL hardware language,this hardware language can be applied to the FPGA platform,finally it can accurately find a reasonable path in the given map.The main work and experiments are summarized as follows:(1)A * algorithm is implemented based on C / C + +,the corresponding program is improved to make it conform to the writing style of Catapult software,and the simulation of hardware synthesis is completed.(2)Improve the data structure and implementation of the algorithm,complete the simulation of hardware synthesis,and get better hardware results.The final hardware results show that it occupies less hardware resources and has less Latency after synthesis,which meets the performance requirements of our synthetic hardware,realize hardware acceleration.