| This thesis addresses the problem of synthesizing high-performance control-intensive and processor-like systems from their high-level descriptions. These systems are characterized by large data paths and large control paths. The goal of the synthesis system is to reduce the delay of the critical path, consisting of the combined control/data path.;A judicious choice of the system clock frequency can help in reducing the data path delays. This usually means the use of a fast clock. While a fast clock may reduce the data path delay, it usually increases the number of control states, and hence increases the control area and delay. The use of a pipelined controller may alleviate this problem by removing the control delays from the critical path. However, this may increase the data path delay with the introduction of branch delay slots. A global scheduling algorithm that can find operations to move into these branch delay slots may help in reducing the data path delays. Due to these interactions between the data path and the control path, tradeoffs should be made between the data path and the control path with the goal of reducing their combined delay.;The solution to this problem requires the solution of several subproblems. These are identified as: cycle time selection, control style selection, data path scheduling, data path pipelining and control generation. This thesis describes heuristic algorithms to solve each of these problems. These algorithms generate excellent results when used independently. They can easily be integrated into a generic high-level synthesis system.;However, the algorithms must be used in conjunction with one another with the goal of reducing the combined control/data path delay. Each phase of this combined system now depends on results obtained from other phases. Since there are complex, cyclic dependencies between the subproblems, an iterative, feedback-driven approach is used.;The algorithms have been implemented and incorporated into the high-level synthesis system SandS. The output of SandS is a register-transfer level description of the data path and a gate level description of the control path. The results have shown that the algorithms developed are very effective in synthesizing control-intensive behavioral descriptions. |
