Design And Implementation Of Core IP Core Of Waveform Generation Module Based On Functional Programming

Waveform generator is a commonly used signal source.Because of its flexible waveform signal generation method,it is widely used in electronic circuits and automatic control systems.The waveform generation module,as a functional module for the waveform generator to generate waveform data,is usually composed of the waveform generation core IP core of the two modules: data address generation and data processing and control.It needs to complete the corresponding waveform generation,waveform data processing and other functions according to the needs of users.And how to quickly realize the parameterized waveform generation core IP core has become a major difficulty in realizing the waveform generation module.Compared with using hardware description language to realize the waveform generation core IP core parameterization ability is poor,This thesis presents an IP core design and implementation scheme based on the Spinal HDL library of the functional programming language Scala.Spinal HDL brings the software characteristics of the functional programming language into the hardware logic design,with high-order function operations and powerful parameterization capabilities,which improves the efficiency of hardware logic design.The main tasks completed in this thesis are as follows:1)Spinal HDL is used to design and realize the core IP cores of the data address generation module,such as synthetic command controller,command parser,command executor,command decoder,and DMA controller;To design and realize the core IP of data processing and control module Cores such as distortion signal synthesizer,AXI4-Lite to SPI controller and output controller.These IP cores have been parameterized design,and the corresponding parameterized configuration can be completed according to actual needs.And by these waveform generator core IP cores,a sequence waveform generation module and a distortion signal generation module are formed.2)In response to the requirement that the sequence waveform generation module can generate repeated sequence waves and enhanced sequence waves,the synthesis command controller,command parser and other related IP cores in this design can control the generation of sequence waves and enhanced sequence waves in the form of instructions.Aiming at the requirement of adjustable data throughput,the sequence waveform generation module of this design can realize dynamic adjustment of32-1024 bit data width under the condition of working frequency of 250 MHz to complete different data throughput settings.3)In response to the requirement that the distortion signal generation module can perform amplitude control and waveform superposition of multiple harmonics,the distortion signal synthesizer in this design realizes 8 independently configurable signal channels at a working frequency of 200 MHz.Generate signals of different frequency points by setting different frequency control words,set different scaling factors to amplify and attenuate the signal,and finally synthesize the input signal with a variable number of channels.4)Simulation and testing of the core waveform generator module IP core was completed,and experimental verification of the basic waveform segment and sequence waveform generation was carried out on the sequence waveform generator IP core,as well as experimental verification of the spot frequency signal and distortion signal generation on the distortion signal generator IP core.