Design And Verification Of A Physical Layer Link Of A 50MHz Bandwidth And Low Power Consumption Body Area Network

Body area network is a miniaturized network composed of wearable or embedded devices centered on the human body.It is currently widely used in human health detection and has broad application prospects in consumer electronics,entertainment,military and other fields in the future.As people's lives become more and more colorful,and people's demand for communication bandwidth is getting higher and higher,broadband body area networks have become a research focus.Today,when the development of battery technology encounters a bottleneck,one of the problems of miniaturized wearable devices is that their battery life is relatively short.How to better reduce the power consumption of the device has become a research hotspot in today's society.In this context,this article focuses on a 50 MHz bandwidth low-power body area network physical layer link research and design and verification on FPGA.The main work of the thesis is as follows:First,determine the performance index of the physical layer link of the body area network,and analyze and select its technical implementation plan.According to the specific application scenarios of this subject,a demand analysis was carried out,and the performance indicators and technical options of the physical layer link were determined.Second,design the physical layer link of the 50 MHz bandwidth and low power consumption body area network as a whole.From the overall framework,baseband design,transmitter design,receiver design and low-power design,the physical layer link of the 50 MHz bandwidth low-power body area network is analyzed and designed.Third,the physical layer link of the 50 MHz bandwidth and low power consumption body area network is designed and implemented from several key modules.Starting with several key modules such as Turbo encoding and decoding,time-frequency synchronization,etc.,the 50 MHz bandwidth low-power body area network physical layer link was designed and implemented from the principles of algorithm,interface design,timing design,and implementation.Fourth,complete the test and verification of the physical layer link of the 50 MHz bandwidth and low power consumption body area network through the FPGA platform.The 50 MHz bandwidth low-power body area network physical layer link was tested and verified through the FPGA platform.The test results show that the link meets the performance indicators,and the power consumption is reduced by about 20% after the low-power design.This paper analyzes,designs and implements a 50 MHz bandwidth low-power body area network physical layer link,and tests and verifies it through the FPGA platform,which is a related research on the low-power body area network physical layer link Provides a theoretical and engineering basis.