Research On Key Technologies Of Low Feedback Sampling Rate Digital Predistortion System

The rapid development of wireless communication requires wider bandwidth,and the bandwidth of a power amplifier(PA)output signal expands the original signal by 3-5times,which makes it difficult to ADC sampling the feedback path of the digital predistortion(DPD)system.In addition,the development trend of base station system miniaturization also puts forward higher efficiency requirements for signal processing algorithms in the realization of digital predistortion system.Based on this background,this thesis mainly studies loop delay estimation algorithm and low feedback sampling technique in digital predistortion system.Firstly,this thesis introduces the process of using digital predistortion technology to perform nonlinear compensation on power amplifier,including power amplifier feature extraction,DPD model estimation and signal preprocessing.Then,the influence of delay mismatch between input and output feedback signals on DPD performance is analyzed through simulation,and the necessity of delay compensation steps in the implementation of DPD system is clarified.For the purpose of reducing computational complexity,a loop delay estimation algorithm based on sliding window has been proposed in this letter,where the first derivative characteristic of the signal is employed to evaluate the correlation between the input and output feedback signals.Simulation and experimental results show that for the 100 MHz test signal,the proposed algorithm and the traditional cross-correlation based method could align the input and output feedback signals successfully.But in terms of resource consumption,the proposed integer loop delay estimation algorithm could reduce the multiplier by 100% and the adder by approximately88.5 %.This thesis analyzes the existing low-sampling technology,and improves the subNyquist sampling DPD system based on signal aliasing.This low-sampling DPD system directly performs sampling at a lower than the Nyquist sampling rate of the output signal,and then uses the input signal and the aliased output signal for model parameter identification.Due to the different sampling rate of input and output feedback signal,the alignment algorithm is more complex.This thesis proposed two improved low-sampling signal alignment algorithms.Simulation results show that,even if the undersampling factor was set to 80,these two improved algorithms can successfully align the input and low-sampling output signals,and have lower computational complexity than the alignment algorithm in the reference.Afterwards,the predistorter was generated based on the indirect learning structure,and the feasibility of this low-sampling digital predistortion scheme was verified through simulation.In addition,the output feedback signal is captured at low sampling rate based on the FPGA platform.The results show that the two improved low-sampling signal alignment algorithms have the same estimation accuracy as the algorithm in the reference.Using a20 MHz LTE signal to drive the Class J power amplifier,the experimental results based on VSG-VSA test platform show that the ACPR of the low-sampling DPD system output signal can reach below-50 d Bc with only a 12.288 MSPS feedback sampling rate.Further experimental verification on the FPGA platform,using three DPD models to complete the 2 times low-sampling verification of the 40 MHz input signal,and the ACPR were all lower than-48 d Bc.Finally,the experiments in this thesis also show that when the loop delay estimation algorithm has the same delay compensation effect,the same DPD effect can be achieved.