Design And Implementation Of A 10.3125Gbps Transmitter Based On 130nm

In the era of big data,high speed and stability of data transmission as well as low power consumption and small area of chip are required more and more.The main data transmission modes are parallel transmission and serial transmission,among which serial data transmission occupies a dominant position in the current data transmission.Serdes has high-speed,multi-channel,low power consumption and other characteristics,has been widely used in the communication application.The manufacturing process mainly focuses on GaAs process and CMOS process.GaAs process is usually used in ultra-highspeed circuit,but the manufacturing cost is many times that of CMOS process.Therefore,the conventional design is concentrated in CMOS process.However,in order to achieve high-speed transmission,it's recommended to use the CMOS process nodes of 55 nm or below,and the corresponding costs are multiplied.To resolve the above problems,this thesis explores the design of a 10.3125 Gbps Serdes transmitter based on 130 nm process node.The work content mainly includes the following points:1.In principle.This thesis firstly analyzes the structure types commonly used by the transmitter,and then selects the proper structure according to the design requirements of this thesis;Then it introduces how to measure the performance of the transmitter by the eye diagram,jitter and bit error rate.Finally,the key technologies related to the realization of transmitter function are described.2.In circuit design.The main purpose of the circuit is to convert the input 40-bit parallel data into a pair of the differential serial data through the driver.The circuit mainly involves parallel conversion circuit,clock generation circuit,output driver of current mode,de-emphasis circuit and so on.A complete high-speed transmitter circuit also requires the PLL to provide an accurate 10 GHz clock signal,and the bandgap reference to provide a high-precision reference current for the PLL.Finally,according to the simulation model provided by the process factory,each sub-circuit of the transmitter passes the pre-simulation of the function and performance.A top-level simulation is performed after that the blocks achieve the design target.3.Layout design and post-simulation.At first,this thesis analyzes and introduces the difficulties in the process of layout drawing from the three aspects of effect,parasitic effect and failure analysis.Then the layout of the transmitter is drawn with the CMOS130 nm process information and the effects of various effects on the performance and stability of the transmitter must be considered in order to realize the function of the transmitter.After the layout design is completed,the parasitic parameters are extracted for the post-simulation verification.When the post-simulation result is close to the presimulation result,the transmitter circuit can achieve the corresponding design indicators,the performance is stable and the function is normal.The final geometry dimension of the transmitter is 595 um * 190 um.4.In chip testing.A test board with FPGA and the test chip is used to test the characteristics of the transmitter for the compliance test.After comparing the test results with typical parameters of the transmitter,it was concluded that the design reached the expected requirements.