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Design Of Broadband Multi-beamforming Chip Based On Active Delay

Posted on:2020-12-30Degree:MasterType:Thesis
Country:ChinaCandidate:T A LiFull Text:PDF
GTID:2518306518963699Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of wireless communication and broadband data services,spectrum resources are becoming scarcer and scarcer,while high-quality video and audio,as well as the booming Internet of Things technology,have higher requirements for data transmission rate.In order to solve the problem of path loss in high frequency wireless signal transmission,beamforming technology came into being.Beamforming technology is a technique of sidelobe suppression and selectivity in multi-antenna system using variable time delay and gain.It has been widely used in wireless communications,radar and radio astronomy.This paper designs a low-complexity beamforming chip using active true time delay.The chip adopts a network architecture based on current mode logic differential active delay unit.The architecture is suitable for broadband multi-antenna system with multiple outputs,which can spatially filter the input signals into the array,suppress noise and interference,and enhance useful signals.Different from the traditional beam synthesis architecture,this architecture multiplexes the true-time delay units,uses fewer delay units to complete the low complexity design,and uses improved active true-time delay units to ensure stable delay while greatly saving chip area.Compared with the passive true-time delay beamforming chip with four in four out,the area is saved by nearly 75%.The circuit implementation of the chip includes low noise amplifier,active true delay unit,adder and output stage buffer.Low noise amplifier employs noise cancellation technology to reduce noise,and push-pull structure to reduce power consumption.Active inductance peaking technology is used in the true delay unit,which provides zero points,thus increasing bandwidth,eliminating the use of inductance and reducing area.The chip is designed by HHNEC 0.18?m Bi CMOS process,and the layout is completed,whose area is 2.1 mm x 2.26 mm.The simulation results show that in the range of 0.3 to 1 GHz,the beamforming chip supports four inputs and four outputs at the same time.The minimum delay resolution is 70 ps,and the delay accuracy(RMS)is less than 5 ps.For a uniform linear array with an antenna spacing of 9 cm,it can provide four scanning angles of ±45° and ±14°.
Keywords/Search Tags:Beamforming, Active true-time delay unit, Low-Complexity, Directivity
PDF Full Text Request
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