Programmable True Time Delay Array For Multi-antenna Systems

IR-UWB techniques are suitable for high resolution and precise positioning scenarios,such as MIMO antenna array system.This technology is also attractive in short-range wireless communications,especially in energy constraint applications such as wireless sensor networks?WSNs?and wireless body-area networks?WBANs?.TTD elements are key component in realizing the precise scanning angle resolution and wide scanning angle range of beam forming systems.In order to make TTD technology more easily to be integrated in IR-UWB transmitter and reduce design cost,it is of significance to develop a programmable true time delay array circuit with large delay range,precise delay resolution,high group delay plainness,good anti-interference performance and high stability.A digitally controlled TTD programmable array for the 4-channel IR-UWB transmitting systems is presented.The circuit introduces delays between the transmitted signals of four adjacent channels to realize beam shaping.The whole circuit consists of a 4-path cascaded delay chain,two 4-bit switch to voltage converters and four multiplexers.In addition,an input resistor and a NMOS source follower circuit are added to match the input and output of the circuit to 50ohm.The overall architecture adopts fixed number of delay cells in the sequence of equal difference in each delay chain instead of switch-based tuning method to reduce delay jitter.By introducing the concept of relative delay,the contradiction between the delay resolution and the total delay range of the delay circuit is effectively balanced.By introducing path sharing technology,the number of cascaded cells needed in practice is reduced and the circuit structure is simplified.Through cell matching and symmetric loading,the circuit mismatch between different delay cells is reduced and the delay precision is improved.The delay cell adopts an improved current-deficient active inverter delay structure,which has a large delay range and its delay?is controlled by voltage V_ctrltrl changing the circuit current.The fitting relation between control voltage and cell delay is mapped to binary MOS network circuit to form the switch to voltage converter circuit,which has 4-bit control word input.The non-linear relationship between delay and control voltage is transformed into a linear relationship between delay and control word to realize linear programmable delay tuning.The multiplexer circuit consists of two transmission gates and an inverter to promise a large dynamic range.Two different delayed outputs tapped in each cascade delay path are chosen by the multiplexer,expanding the delay range.Under the 0.18?m CMOS process,the core area of the chip is 0.145 mm²,at its total area including the I/O pads,it is 0.39 mm².The pre-simulation results show that in multi-output programmable delay array circuit,the maximum cascade error of a single delay cell is 1.9 ps,where the delay error rate is 0.625%,and the maximum delay error rate caused by control voltage is 3.125ps/V.The maximum delay jitter of delay cell is 4.96%,and the maximum jitter of delay step is 1.68%.The post-simulation results at TT process corner of the designed delay array are as follows.The delay array circuit achieves two delay ranges:0¹95ps and 220ps⁴20ps.These delay ranges can be controlled by a 4-bit switch with?13±1.5?ps delay resolution.The gain jitter of four delayed output signals is less than+0.5%.Flat group delay response is achieved in the bandwidth from 0.2 GHz to 1.2 GHz.In passband,the jitter of the relative delay range of the four-delay output is 10.7%,and the maximum jitter of the relative delay step is 6.85%.The biggest power consumption is 288mW at the voltage 1.8V,divided as 72mW for each delay path.This delay array structure can be easily integrated into multi-antenna systems.Its delay range can provide the scanning angle range of-23°²3°and 26.1°⁵6.1°of the system with antenna spacing d=18 cm,and the scanning angle resolution is about 2.5°.