Design Of Low Intermediate Frequency Broadband Multi-beam Arrays Chip Applying In SKA

With the rapid development of modern communication technology,the requirement of wireless transmission rate is getting higher and higher.In order to meet the different needs of various industries,MIMO(Multi-input Multi-output)technology emerges as the times require.MIMO technology can not only effectively improve the system's channel capacity,but also significantly improve the energy efficiency of wireless systems.Beamformer technology based on MIMO technology can transmit or receive signals directionally.It has been widely used in radar,wireless communication,radio astronomy and other fields.The principle of beamformer technology is to use a phased array so that the signal from the desired direction form a phase interference and the signal from the other direction form a cancellation interference,so as to amplify the signal from a specific direction.Compared with the omnidirectional transceiver system,beamformer technology can significantly improve the transmission or reception gain and system efficiency.Based on the SKA project,this paper designs a wideband multi-beam synthesis chip applying in low intermediate frequency.This chip employs a network-like MIMO architecture,which can support four inputs and four outputs at the same time.The chip's area and power consumption are reduced by highly reusing the delay units.The chip designed in this paper has a working frequency of 0.35-1 GHz.The delay resolution is 80 ps and the maximum group delay is 720 ps when the spacing of four antennas is 10.5 cm.It can provide four scanning angles of ±42° and ±13° to synthesize and amplify spatial signals effectively.The circuit implementation of this chip includes low noise amplifier,true delay cell and buffer.Low noise amplifier employs current multiplexing technology to save power,noise cancellation technology to reduce noise and resistor feedback to achieve broadband input impedance matching.True time delay unit employs analog IC filter architecture.Compared to the traditional LC ladder architecture,filter architecture occupies smaller chip area in the case of the similar delay fluctuations.The buffer uses the common-source and common-drain structure to compensate the insertion loss introduced by the delay unit.At the same time,the isolation between ports is improved and the crosstalk between signals is reduced.This chip is designed and fabricated by TSMC 0.18 um RFCOMS process.Finally,layout and tape-out of the chip are successfully completed.Keysight's vector analyzer is used to test this chip.The test results show that the chip can control the true time delay accurately and superimpose the signals in the same phase.