Design And Performance Improvement Of Floating-point Divider

Floating-point operations have been widely used in many fields such as real-time graphics,multimedia application processing,and digital signal processing.When many digital signal processing algorithms use floating-point operations,they need to perform millions of calculations per second.Such stringent requirements promote the development of circuit design in a faster,more accurate,and more efficient direction,so the research on floating-point operations is particularly important.Traditional floating-point arithmetic processing has more research on single-precision floating-point numbers and double-precision floating-point numbers,but the area and power consumption of these high-precision processing units are correspondingly high.However,for some low-power designs with low precision requirements,high-precision floating-point arithmetic units not only consume more resources,but also affect their operating speed.In order to better solve the above problems,this paper designs a half-precision floatingpoint divider based on the fusion logarithmic converter.The mantissa processing part of the divider uses the idea of logarithmic conversion,through which the complex mantissa division operation can be transformed into a subtraction operation.On the basis of logarithmic conversion,three architectures for the hardware implementation of the divider are proposed.The area,delay and period of the three architectures are analyzed and compared,and finally the fusion logarithmic converter is used to realize the divider.In the design process of the fusion logarithmic converter,this paper first designed the logarithmic converter and the antilogarithmic converter respectively,and then through the analysis of the functional characteristics of the logarithmic function and the antilogarithm function,using the mathematical similarity of the two,creatively proposes the hardware structure of the fusion of the two.That is,weak hardware resources are added on the basis of the logarithmic converter,so that the fusion structure can realize the two functions of logarithmic conversion and antilogarithmic conversion at the same time.This design makes the hardware reusable and achieves the purpose of saving resources.After designing the fusion structure,this article started with the part and the whole,and analyzed the performance of the structure of the fusion logarithmic converter and the whole half-precision floating-point divider respectively.For the fusion logarithmic converter,the comprehensive results of the SMIC.18 process show that the logarithmic converter can realize the antilog function at the cost of 14% of the unit area and 6% of the delay.For the halfprecision floating-point divider as a whole,compared with Xilinx's built-in half-precision floating-point number divider IP core,the main frequency is nearly doubled,the lookup table is reduced by 25%,and the trigger is reduced by 56%.