Equalization Technology And The Design And Implementation Of Its Key Chips For Ultra High Speed Links

With the development of cloud computing,Ethernet and mobile Internet,the desire for high-speed transmission of information is becoming more and more eager.The higher the transmission rate,the more challenging the signal integrity of the serial link is.In most systems,because of the limited bandwidth of communication channel,crosstalk,reflection,jitter and other factors,the overall performance of the link is degraded,which has become the key bottleneck to improve the rate.In order to ensure the low cost of serial link,people usually do not change the material of the channel,but improve and develop link architecture,which poses severe challenges to the design of high-speed circuit and system.In this paper,the equalization technology of ultra-high-speed serial link is studied in depth.The research content is simulated and analyzed.Many high-speed equalizer chips are taped out and verified.In this paper,firstly,the mechanism of skin effect,dielectric loss,crosstalk,jitter and reflection which seriously affect the signal integrity of high-speed serial link and the principles of various equalization techniques are analyzed.At the same time,the structure of transceivers used in serial link at different rates is discussed.The characteristics of NRZ,PAM-4 and Duobinary are compared and analyzed.For the serial link of 25 Gb/s NRZ signal,the influence of various factors on the link performance is analyzed by simulation.In this paper,an equalizer based on Duobinary signal is constructed by combining FIR filter with channel.The tap number and tap coefficients of FIR filter at the transmitter are determined by link simulation,which lays a solid theoretical foundation for the circuit design of the high-speed equalizer in later paper.Based on the link simulation of equalizer based on Duobinary signal,a 10 Gb/s equalizer based on Duobinary signal is designed by 0.18?m CMOS technology.In order to solve the bandwidth problem of the active delay unit,the attenuation technology of source-level capacitance is used to design the delay unit.In order to solve the delay accuracy of active delay unit which is easily affected by process,voltage and temperature,the technology of load resistance calibration and variable capacitance calibration are adopted to improve the flatness of group delay at different process corner.On this basis,the designed 6-tap FIR filter is taped out and verified.The test results show that the signal obtained by the 10 Gb/s ideal PRBS31 signal passed through the FIR filter chip and the FR4 backplane channel with 16.25 dB loss at Nyquist frequency is the Duobinary signal.Aiming at the high-speed serial link with high loss,a high-speed equalizer combined by adaptive CTLE + adaptive DFE is designed by 0.13?m BiCMOS process.Adaptive CTLE with intermediate frequency compensation expands the range of frequency compensation to the mid-frequency band,which solves the problem that traditional CTLE can only compensate in the low and high frequency,and cannot compensate in the mid-frequency.It effectively eliminates the tail of impulse response,improves the eye opening,and reduces the burden of DFE.In order to improve the adaptive ability of DFE,the LMS algorithm implemented by full analog circuit is used to update tap coefficients of DFE in real time,and the half-rate speculation structure of DFE is used to reduce the delay of critical feedback path.The measured results of high-speed adaptive equalizer combined by CTLE+DFE show that the maximum speed of the signal equalized which passed through the Rogers backplane and the equalizer chip reaches 33 Gb/s,and a good eye opening can be obtained.The loss can be compensated up to 22 dB at Nyquist frequency.In order to explore signal integrity of the high-speed serial signal over 25 Gb/s in high-loss channel such as backplane,the partial response maximum likelihood(PRML)equalization based on sequence detection,which can achieve a compromise between high-speed and low bit error rate(BER),are studied in this paper.In order to solve the problem that the filter coefficients of PRML equalization need to be obtained by adaptive DFE,the PRML based on noise prediction(NPML)is discussed in this paper.On the basis of PR2,the filter coefficients of partial response are obtained by noise prediction.The performance and hardware resource consumption of DFE,PRML and NPML equalization are analyzed by simulation,which provides theoretical and practical basis for future partial response maximum likelihood equalization.Finally,the hardware implementation of Viterbi decoder,the key module of PRML equalizer is studied.The data processing capability of Viterbi decoder is improved by independent forward sliding block which transforms the continuous data stream into independent data blocks and process in parallel between blocks.In order to solve the problem that the pipeline technology cannot be introduced by the ACS recursive structure of independent forward sliding block,the improved partial adder(MPFA)is used to construct the parallel “addition” and “comparison” of ACS structure from the point of bit level.Finally,the independent forward sliding block based on ACS deployment structure and the independent forward sliding block based on ACS recursive structure are synthesized and simulated.The results show that the clock frequency of the former is 500 MHz,and the latter is 210 MHz.This paper has important theoretical and practical significance for ultra-high-speed links in the future.It can not only promote the further development of ultra-high-speed communication systems,but also play a powerful role in promoting the design of high-speed communication integrated circuits in China.