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Study On Nano-computing Architecture And Fault-tolerant Techniques

Posted on:2021-06-04Degree:MasterType:Thesis
Country:ChinaCandidate:H Y DouFull Text:PDF
GTID:2518306503464854Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
With the scaling of complementary metal oxide semiconductor(CMOS),Beyond CMOS is thought to be a significant complement to CMOS in the future.Nanodevices play an important role in this process,and nanodevices including Carbon Nanotube Transistor FET(CNT FET),Resistive Random Access Memory(RRAM),Tunneling FET and Spintronic devices own the advantages like small area cost,small power-delay product,non-volatile,and high mobility which traditional CMOS doesn't have.Due to their special manufacture methods,they intend to be defective.This thesis proposes a new fault-tolerant architecture FT-FPNI based on field-programmable nanowire interconnects.This architecture consists of one nanowire interconnect layer and one nanodevices logic layer.Vias are used to connect these two layers.The input nanowires and output nanowires are connected by resistance random access memory(RRAM),whose resistance is controlled by voltages applied to them.The nanodevices logic layer is composed of nanodevices,and fixed number of nanodevices build the basic logic unit.At the defects check stage,faulty logic units will be picked out,and the corresponding RRAMs will burn out.At the circuit function configuration stage,the resistance of corresponding RRAMs will be modified to determine the connection between logic units.CNT FET and RRAM are studied as typical nanodevices.First,the properties and advantages of CNT NOR gate and RRAM LUT are analyzed.Then based on this,the defects check and circuits configuration process are demonstrated.With the defect injection technique based on Verilog HDL,this thesis use Quartus II + Model Sim&FPGA to verificate the FT-FPNI.The FT-FPNI can detect defects at 100% rate.The delay of CNT NOR is as low as2.89 ps and its power consumption is as low as 6.789 p W,reduced by two orders of magnitude comparing with state-of-the-art CMOS techniques.Finally,this thesis compares the performance of FT-FPNI with traditional TMR-MAJ technique.FT-FPNI reduces 53% area cost and maintain its 100%defects detect rate while the TMR-MAJ fails.
Keywords/Search Tags:nanodevices, FPNI, fault-tolerant
PDF Full Text Request
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