Design And Analysis Of 1700V Sic MOSFET And Its UIS Characteristics

Silicon carbide?SiC?is the third generation wide-band-gap semiconductor material.The metal oxide semiconductor field effect transistor?MOSFET?based on SiC has superior performance.In the field of power conversion,MOSFET has external or parasitic inductive load.When the circuit is turned on,the energy is stored in the inductor.When it turns off,the energy is released through the power device,which forces the device to avalanche.The high voltage and current will cause serious impact on the device and the device will fail.It is worth noting that the dielectric constant of SiC is about three times than that of SiO₂,as a result,the electric field of oxide is much higher under avalanche,which means SiC MOSFET has severe reliability challenges.The unclampled inductive switching?UIS?can simulate the extreme electrical stress in the system application,and can be used to evaluate the avalanche energy of the equipment.Therefore,it is very essential to study the dynamic characteristics of UIS to improve the stability and reliability of the system.In this paper,we design and optimize the basic physical parameters of the 1700V planar SiC MOSFET device,including structure parameters,like doping concentration of drift region,injection energy and dose of N⁺contact region,P⁺contact region and Pbase region,width and doping concentration of JFET region.Besides,the on-resistance(R_ON),breakdown voltage and other static characteristics are concerned.The structure parameters are as follows.The drift region doping concentration and thickness are 6e15cm^-33 and 14?m,respectively.The width of JFET region is 2?m,and the thickness of gate oxide is 60nm,Then,the field limiting ring?FLR?structure is studied,which is divided into multi-regions with varying space,and the blocking voltage of 2180V is obtained.Then,we aim at the structure characteristics of devices and the failure mechanism of UIS test,including the influence of different structures and circuit parameters on their electrical properties.In order to get a better performance,a trench P⁺source MOSFET structure is designed as an improved structure.When the depth of the P⁺contact groove is 0.8?m,the current path is effectively transferred,under the avalanche condition,from the corner of Pbase/N-drift to the bottom of the P⁺source.By reducing the density of SiC/SiO₂ interface during the UIS test,the maximum electric field of the gate oxide during avalanche is reduced by 15%compared with that of planar MOSFET,which indicates that the trench P⁺-source MOSFET structure improves the reliability of gate oxide during the UIS test.Finally,according to the structure parameters of SiC MOSFET devices,the process flow and layouts of the proposed structure are designed,which is based on the domestic SiC MOSFET process platform,and the experiment is carried out.The threshold voltage is 3V.When V_GS=22V,V_DS=2.5V,the drain current I_DSS reaches 15A,the specific on-resistance is 16.7m?·cm².The breakdown voltage is 1850V,compared with the ideal parallel plate junction,terminal efficiency reaches 84%.Through the design of1700V SiC MOSFET and the study of its UIS characteristics,this paper provides the theoretical basis and guidance for the development of 1700V SiC MOSFET with high reliability.