Study On Dynamic Reliability For SiC MOSFET

Due to superior material properties,SiC MOSFETs is considered as a promising competitor in high power electronics fields.SiC MOSFETs typically have high voltage,high frequency,low loss and high temperature and other superior performance,which can significantly improve the efficiency and power density of power system.At present,many semiconductor companies have successively launched commercial SiC MOSFETs products and have gradually begun to replace Si-based power devices in electric vehicles and photovoltaic inverters fields.In order to reduce the on-resistance of planar gate SiC MOSFET devices,some manufacturers have developed trench gate SiC MOSFETs devices.By reducing the cell pitch to increase the power density and significantly improve the SiC MOSFETs switching characteristics.Although the research on SiC MOSFETs has made great progress,there are still some key technical bottlenecks need to be overcome.The SiC MOSFETs dynamic reliability needs to be solved urgently,such as unclamped inductive switching(UIS)and Short circuit(SC).Owing to the differences in materials and device structure,previous research on Si-based MOSFETs dynamic reliability cannot be directly applied to SiC MOSFETs.Therefore,SiC MOSFETs dynamic reliability has become one of research hotspots in power semiconductor devices fields.In this paper,the dynamic reliability test platform and the semiconductor numerical analysis tool Synopsys Sentaurus TCAD system are used to study unclamped inductive load switching and short-circuit during SiC MOSFETs dynamic switching.The physical behavior image and failure mechanism during dynamic switching are discussed,the internal physical mechanism of UIS and short-circuit failure and the key factors affecting the robustness of the device are clarified,which has a good promotion for the design and application of SiC MOSFETs.Firstly,a 1200 V SiC MOSFET dynamic reliability test platform is designed and built.Based on this platform,two trench gate SiC MOSFETs with different shielded structure under UIS condition are compared by experiment,and avalanche robustness of the devices at different temperatures are evaluated.Secondly,by monitoring DC parameters,device numerical analysis and post decapsulation and other methods to confirm UIS failure mechanism.Experimental and simulation results show asymmetric trench SiC MOSFETs can effectively protect the gate under avalanche conditon,and the failure mode is thermal runaway.For double trench gate SiC MOSFETs,two failure mechanisms are identified,i.e.thermal runaway and gate oxide rupture.The gate oxide damage is confirmed at room temperature;thermal runaway is confirmes at elevated temperature.The gate oxide failure mode indicates source trench could not relieve the gate oxide electric field crowding at the corner of the trench bottom during the UIS stress.Finally,this paper investigates 1200 V planar SiC MOSFETs short-circuit behaviours,including failure modes and physical mechanisms.Due to the sharp rise in chip temperature during short circuit,the threshold voltage decreases and thermally generated carriers are main causes of current slope change,current tail,and failure.Considering SiC MOSFETs short-circuit tolerance is affected by the rising chip temperature,various circuit parameters affecting SiC MOSFETs short-circuit are studied,including stray inductance,gate resistance,power supply voltage and gate voltage,etc.In this work,through experiment and finite-element simulation,the unclamped inductive switching and short-circuit dynamic reliability of SiC MOSFETs are evaluated.The trench gate SiC MOSFETs avalanche failure modes with different structure and planar gate SiC MOSFETs short-circuit tolerance are investigated.The results in this thesis can not only provide reference for device selection and circuit design in practical applications to prevent dynamic failure,but also provide theoretical guidance for further improving SiC MOSFETs dynamic reliability.