JPEG2000 Lossless Compressor Implemented By Multi-core Heterogeneous Architecture

With the development of science and technology, the amount of data in human life is increasing, and the algorithm of data center is becoming more complex. As a result, single-core CPU can't satisfy the demand of people on the system performance. Multi-core heterogeneous systems which integrates a large number of general-purpose processor, GPU, DSP and other IP cores, has many advantages, such as high performance, low power consumption and short development cycle. Thus, in the field of intensive data and intensive computation, multi-core heterogeneous system has achieved significant effect.In recent years, JPEG2000 lossless compression has been widely used in the field of space remote sensing image application and medical image, the related research is also gaining more and more attention. But, in the existing implementation schemes, there is still many contradictions between the performance and the development cycle, as well as the performance and the cost. Therefore, it is meaningful to study how multi-core heterogeneous system to improve the performance of JPEG2000 lossless compression with reducing development cycle and cost.This paper divides the JPEG2000 into a set of hardware and software modules, based on the algorithm. Since the wavelet transform module and the TIER-1 module cost more time to encoder, they are implemented in FPGA hardware, while other modules are implemented by the open source software, Jasper. Consulting OpenCL platform model, This paper proposes a kind of multi-core heterogeneous platforms which is applied to the JPEG2000 encoder. The platform links the main processor, cell and storage through the AXI bus. The main processor is responsible for the task scheduling and monitoring, and the JPEG2000 modules are processing elements in the computing units. Each processing element owns private memory.After introducing the multi-core heterogeneous platform, this paper focuses on the design of the wavelet transform and TIER-1 hardware processing elements. In the wavelet transform, the line-based wavelet transform and the column-based wavelet transform are parallel processing, so as to achieve the goal of the hardware acceleration. The TIER-1 moduleincludes a fully parallel bit plane coding module and multiple MQ coding modules, which adopt four pipeline architectures.In order to solve the problem that the rate of the MQ coding does not match the rate of the bit plane coding, this paper uses a MQ coding, following every bit plane coding pass.At the same time, this paper adopts the thought of skipping invalid data to improve the speed of the TIER-1 module at the extreme.The multi-core heterogeneous platform is implemented on the Xilinx development board VC707. Design and simulate the hardware accelerations with ISE development suites, and then the hardware accelerations are integrated into the EDK tools. The platform is verified for 512 x 512 grayscale image at 69 frames on FPGA with 100 MHz, which can meet the requirement of real-time. In addition, the platform provides users with API functions for software programming. Based on this platform, users can easily implement JPEG2000 encoding only by inputting the corresponding function in the software. This way can greatly reduce the development difficulty and cycle.