DFT Design And Verification Of A Motor Code Disc Control Chip

With the rapid development of integrated circuit design levels and manufacturing processes,the scale and design complexity of chips have increased dramatically,and the clock frequency of chips has continued to increase,which has challenged the testing of chips.Design for testability(DFT,Design for Testability)has become a very necessary part of the design and manufacturing process of the chip.The significance of DFT technology is that it can reduce the time to market(TTM),reduce the cost of testing and improve the quality of products.Based on the physical design and implementation of a motor code disk control chip,the testability design of the chip was researched and verified.Based on the basic theory of DFT,the DFT design methods used mainly include scan design method,memory build-in self test(MBIST)design method,and boundary scan design method.These design methods provide a convenient and feasible test solution for the code disk control chip.In this paper,after briefly summarizing the basic theory of testability design,the failure model of the chip and the corresponding test vectors,the specific contents of the development are as follows:(1)Carry out the full scan design of module level and TOP level for the code disk control chip.After analysis of the results,the Stuck-at fault coverage of the module-level scan design is about 97%,the TOP-level Stuck-at fault coverage is about 90%,and the TOP-level Transition fault coverage is 96%.(2)For the memory of the code disk control chip,a new method to reduce the power consumption of MBIST is adopted.This method divides the memory into groups according to different clock domains and different memories.The serial operation is performed during the time,and the parallel operation is performed within the group.The results show that this method makes the test power consumption only35.69% of the traditional test power consumption and the test time is only 25.5% of the traditional test time.