Research On ESD Protection Of Tunnel FET Based On 3D TCAD

With the rapid development of semiconductor integration circuit(IC)technology,the die size of devices is becoming smaller and smaller.As basic unit of IC,the metal-oxide-semiconductor field-effect Transistor(MOSFET)has been reduced to a nanometer process.However,with the reduction of device size,there are a lot of problems such as higher production process cost,higher power consumption,and gradual degradation of reliability.The leakage problem is common in MOSFET,with the main reason is that MOSFET can not break through the subthreshold swing limit of 60mV/dec at room temperature.In the past decade,there has been extensive researches on devices based on new physical mechanisms,such as Ferroelectric FET(FE FET),Impact Ionization MOSFET(I-MOS),Tunnel FET(TFET)and so on.TFET based on the quantum tunneling principle can theoretically obtain the subthreshold swing lower than 60mV/dec,thus effectively reducing the leakage current and power consumption.TFET,as an alternative device replaced MOSFET,has become one of the research hotspots in the field of microelectronics.However,one of the main factors affecting the reliability of integrated circuits is Electrostatic discharge(ESD).Devices with low power consumption,small size and new technology bring greater challenges to ESD protection.The physical process of TFET under ESD impact is a problem worthy of further study.The work of this paper is as follows:First,based on previous research results of TFET devices,this paper analyzed the tunneling and self-depletion mechanisms in the T-gate Schottky Barrier Tunnel FET(TSB TFET),modeled it in the Sentaurus TCAD,simulated its DC characteristics,and calibrated it with the data in the literature.The simulation results show that the Schottky Barrier tunneling mechanism significantly increases the opening current,the self-depletion effect reduces the leakage current,and the T-gate structure enhances the surface electric field.Second,this paper simulated n-type MOSFET,n-type TFET and Schottky Barrier MOSFET(SB MOS)with the same size as TSB TFET,and compared four devices to explore the influence of barrier height and depletion degree on on-state current and leakage current.Finally,by comparing the Ion/Ioff of TSB TFET and SB MOS,the ideal design parameters of TSB TFET are obtained.Third,based on the DC characteristics of TSB TFET,3D TCAD was used for the first time to simulate the device response process of TSB TFET,Under ESD stress,the electrothermal characteristics of TSB TFET involved in the process were analyzed.The physical mechanisms involved in the ESD phenomenon are complex.The TLP ?-?characteristics of TSB TFET with gate grounded are calculated.The curve has snapback phenomenon,which proves that TSB TFET is snapback ESD protection device.In this paper,the process of junction breakdown,avalanche breakdown,holding and failure in detail.Finally,the influence of TSB TFET device parameters on ESD protection performance is discussed.Compared with traditional 2D devices,TSB TFETs have more 3D structural parameters.The influences of gate finger width(Wf),gate finger length(Lf),gate drain distance(DOP)and drain doping concentration on ESD design window were studied.Consequently,the design direction of TSB TFET as ESD protective device is given.The innovations of this paper are as follows:Firstly,the ?-? characteristic curve of TSB TFET under ESD is modeled and simulated,which proves that TSB TFET is a snapback ESD protection device.The analyzation of electrothermal characteristics of TSB TFET under ESD impact is given in this paper,including junction breakdown,device conduction,snapback and failure.It is proved that TSB TFET has good ESD protection ability.Secondly,the influence of TFET structure on ESD protection ability was explored,and the design rules was given according to the requirements of ESD design window.It is proved that the larger T-gate provides the larger the area of current.That is the thermal failure is not easy to occur.The concentration of drain doping and the distance between drain and gate can significantly influence trigger voltage.If the VDD of the protected circuit is known,the appropriate trigger voltage can be obtained by changing the drain doping concentration and the distance between the drain and the gate.Better ESD protection performance of TSB TFET can be designed by following this rule.