PCIe Data Compression Accelerator Card Based On FPGA

With the advent of the cloud era,data compression technology plays an increasingly important role in various fields.This technology is used in data transmission field to increase the transmission rate and reduce transmission delay.Another field where data compression used is data storage,which uses to improve storage media utilization and reduce storage costs.As a classic lossless compression algorithm,Deflate algorithm compresses the original data twice by combining dictionary encoding and Huffman encoding,which effectively reduces the file size.Though the excellent compression performance the Deflate algorithm possess,the large memory space occupation and CPU computing power consuming during compression process are intolerable draw backs.Due to the low performance of the Deflate algorithm software implementation,this paper proposed a heterogeneous acceleration scheme based on FPGA to meet the requirement of high bandwidth and low latency of this algorithm.This design implements parallel acceleration of the Deflate compression algorithm by utilizing the flexible structure and powerful computing power of FPGA.The decoupling of the origin data block in data compression is achieved by limiting the string match distance at the cost of a part of compression rate.A dynamic depth hash table structure is proposed to achieve the parallel characteristics of Deflate compression engine,cooperates with the control module and several matching units to perform parallel matching on strings at multiple positions.To efficiently process the data in triad structure after dictionary encoding,this paper proposed an efficient Huffman encoding and Deflate packing architecture which can processes triad elements in the same time.This paper uses Verilog HDL to implement Deflate compression engine,the maximum operating frequency is 265.11 MHz.When the system frequency is 250 MHz,the compression speed of a single Deflate compression engine on Silesia corpus is about 347.5 MB/s,which is about 3 times faster than the software implementation under Intel Core i9-9900k@5GHz.The digital circuit designed and implemented at the expense of part of the compression rate has greatly improved the speed of the Deflate Compression algorithm,which meets the high bandwidth and low latency requirement of data transmission and storage in the cloud era,and has achieved the research of this subject propose.