Research And Implementation Of H.265 Inter-frame Coding Based On FPGA

As a new generation video coding standard,H.265 is mainly for high-quality(HD,4K/8K)video applications.H.265 has better coding performance than previous video coding standards,which is currently one of the most popular international video coding standards.On the basis of H.264,H.265’s compression rate is doubled with the cost of a substantial increase in coding complexity.Therefore,the optimization and improvement of the algorithm in the H.265 coding standard has very important research significance.H.265 often has the disadvantages of large encoding delay,low data throughput rate,and low efficiency in software implementation.And it is difficult to meet the real-time requirements of video.As the most computationally intensive part of video coding,inter-frame coding accounts for about70% of its computation.The efficiency of inter-frame coding directly affects the efficiency of the entire video coding.It’s become an important research direction to use hardware to accelerate video inter-frame coding.This paper focuses on the algorithm design of the H.265 inter-frame coding part and the hardware implementation of FPGA.The main contents of this paper are as follows:Firstly,this paper studies the basic framework of H.265 video coding and the key technology algorithms of inter-frame coding.On the basis of the original hardware structure,an improved twodimensional systolic array motion estimation hardware structure based on the full search and matching algorithm of inter-frame coding is proposed.This structure can be adapted by increasing or decreasing the data delay between different processing units.The matching operation when the current block is at different positions can better improve the quality of the inter-frame prediction coding of the edge pixel block.In addition,this paper also completed the FPGA hardware implementation process of the inter-frame coding module including the storage and acquisition of video image data,the motion estimation of inter-frame coding,the calculation of motion vectors,the transformation and quantization of residual coefficients.This paper has used Verilog HDL hardware description language to design the entire inter-frame coding module,and used the verification simulation tool to simulate and verify the entire module,verified the feasibility of the whole module.Finally,the entire inter-frame encoding module is synthesized on FPGA.The architecture can achieve1080p@76fps video image encoding performance,the highest system clock frequency is 250.6MHz.The rate and quality of inter-frame coding have been greatly improved.