Design Of Wireless Terminal Low Power Encoder For Industrial IoT

With the rapid development of the Industrial Internet of Things,traditional industries have begun to develop in an intelligent direction.In this process,wireless transmission of information between levels has higher requirements for reliability and timeliness.In wireless communication systems,channel coding and decoding have the functions of checking and correcting errors.Therefore,the anti-interference ability in channel transmission can be improved,the bit error rate can be reduced,and the reliability of information can be improved.Because the encoder is an indispensable part of the wireless communication system,and its functions are more complicated,it becomes the mainstream practice to integrate the encoder into the digital circuit after hardware implementation.With the increasing integration of digital integrated circuits,the chip's power consumption is getting larger and larger,and even its performance will be affected.It also brings great challenges to chip packaging technology and power supply manufacturing technology.Therefore,the design of low-power encoders plays an important role in reducing chip power consumption and improving chip performance.It has greater guarantee for the reliability and timeliness of information transmission,and is of great significance to the intelligent development of industry.This paper studies the working principle of channel coding and the source of integrated circuit power consumption,and implements channel coding in hardware using Verilog language.The module reuse method is adopted in the architecture design to minimize the consumption of resources to reduce power consumption and improve performance.In addition,the top-level design of the encoder also incorporates a gated clock low-power technology,which directly shuts off the clock signal of the non-working state module from the top-level root,minimizing the invalid flip inside the module,thereby reducing the encoder.Dynamic power consumption.In order to verify the correctness of the encoder function,a simulation verification environment is set up under Linux system.The simulation verification results show that the encoder function is correct.Finally,this article did a front-end flow process,including DC synthesis,PTPX timing analysis,Formality verification,Spyglass inspection,performance analysis of the encoder's power consumption,frequency,area,and throughput to achieve the expected performance indicators,and the output gate-level netlist is available for back-end use.