Optimization On Buffer Management And Flash Translation Layer Algorithm For Solid State Drive

With the development of chip manufacturing technology,the computer's CPU performance has been rapidly improved,but the gap between the IO and CPU processing performance has gradually widened.The traditional disk IO processing speed seriously restricts the overall performance of the computer to further improve.Compared with the traditional mechanical disk,SSD has the advantages of low delay,low energy consumption and high reliability.Currently,SSD has been widely used in many industries.However,SSD also has some defects,such as asymmetric reading and writing,limited erasure times and erasure before writing.In response to the above defects,technical researchers have optimized the solid-state drive firmware algorithm to reduce the impact of these defects.However,the current technology targets different application scenarios and different focuses,which cannot be applied to complex and variable load environments on a large scale.This paper optimizes the design of the algorithm from the buffer management algorithm and the flash translation layer algorithm to achieve the purpose of improving the storage performance of the solid state drive.The main work includes the following two aspects:1.In the optimization design of the buffer management algorithm,this thesis proposed a hybrid storage buffer management algorithm(HSBM).HSBM uses DRAM and NVM as physical storage media,which is mainly used to cache random writes and sequences writes with different update data.And through the migration mechanism,the data pages of the second are dynamically migrated to DRAM in NVM.When the data pages of DRAM are deleted,the strategy of clustering into blocks is used to write the deleted dirty pages to the corresponding data blocks of NVM,so as to convert the random write requests into sequential write requests.When the NVM data block is removed,the dirty page filling technology is used to merge and fill the data block with the data page attached to the data block in DRAM and write it back to flash memory.The auxiliary data page of the data block is not removed in DRAM,but its status is changed from dirty page to clean page.Experimental results show that the HSBM can effectively improve the hit rate of the cache area,reduce the block erase counts,and reduce the average request response time.2.In the optimization design of FTL,This thesis proposes a flash translation layer algorithm DPFTL by classifying the address mapping table.In order to keep the frequently accessed mapping items in the cache,DPFTL sets the hot mapping table and the cold mapping table in the cache area,which are mainly used to cache the address mapping information of different access frequencies.In order to increase the chance of address mapping entries remaining in the cache area,the algorithm additionally sets up replacement address mapping tables,which are mainly used to cache the address mapping entries that have been updated from the hot mapping table and the cold mapping table.When excluding address mapping items,the idea of clustering is adopted,and the address mapping is written back to the translation page of the flash memory in the form of "cluster",which can effectively reduce frequent excluding address mapping entries.The experimental results show that the DPFTL has greatly improved the indicators of buffer hit ratio,average request response time,block erase counts and operation counts of translation pages.