Design And Optimization Of Flash Translation Layer For SSD

As a large-capacity storage media,SSD has many benefits such as faster accesstimes, low energy consumption, Shock anti-throw, etc.The performance of SSDdepends on flash memory chip,firmware and main control chip. The master chipinterface speed is one of the main factors to improve SSD performance; Firmware offlash translation layer (FTL) is usually employed to hide the characteristics of NANDflash memory as to Upward-compatible file system.Selecting Xilinx high-performance Virtex Series FPGAs as the main control chipof SSD. Transplanted microprocessor MicroBlaze, connected each functional modulethrough the on-chip bus AXI to build a solid-state disk controller SOPC systemarchitecture.Designing and implementing the FTL based on SOPC of SSD system. The FTLprovides many functions: The command transmitted by the file system is passed to theflash control by the command parsing and address mapping; Reduced the overhead ofaccessing flash directly by buffer management; Through Garbage collection and badblock management to control and manage the space of flash memory chips.Theexperimental results verify the basic functions of FTL.The performance of the SSD mostly depends on the performance of FTL,in orderto improve the performance of SSD, proposing an improved LRU algorithm of FTL:The improved LRU algorithm based on hot/cold data attributes and update propertiesto select a replacement node. We runed real trace on the solid state disk(SSDsim), theexperimental results show that the buffer hit rate, times of erasering operate, and theaverage response time of improved LRU algorithm has improved compared to LRUalgorithm and CFLRU algorithm.