Research On Packaging Degradation Mechanisms And Coupling Failure Behaviors Of SiC MOSFET Power Module

With the rapid development of applications in photovoltaics,new-energy vehicles and other fields,Silicon Carbide based Metal Oxide Semiconductor Field Effect Transistor（SiC MOSFET）is accelerating to replace the silicon-based power devices because of its excellent characteristics such as wide band gap,fast switching speed,high temperature resistance and low loss.However,the high-reliability requirement of SiC MOSFET power module has become the key factor restricting its large-scale applications.Therefore,it is urgent to carry out profound study on its reliability mechanism and failure behavior of SiC MOSFET power module.At present,the damage mechanisms of the packaging in the presence of void defects and microcracks are unclear,and the research on the coupling failure behaviors of multi-characteristics and uneven electrothermal distribution in SiC MOSFET power modules is still lack.This thesis explores the thermal behavior and degradation mechanism of mechanical properties of the die-attach layer.Then,in the module level,this article elucidates the competitive mechanism of SiC chip-packaging coupling failure and the coupling mechanism of electro-thermal imbalance for the multi-chip parallelled module The main tasks are as follows:1.The thermal characteristics of randomly distributed voids in the die-attach solder layer in the power module were investigated through numerical simulation.The S_max value reflecting the local void ratio of the die-attach layer with randomly distributed voids is proposed,which has a good linear relationship with the module junction temperature and can achieve 92.4%accuracy in predicting the hot spot location of the power module.In addition,it is found that the upper limit of the voids radius has a significant effect on the junction temperature in randomly distributed voids.2.The life of solder layers with different void configurations is evaluated based on the fatigue-creep coupled damage.Besides,a new calculation method of creep lifetime by using dynamic creep rate under the temperature mission profile is proposed.With the increase of the void ratio of the solder layer,the lifetime of the module decreases sharply.When the void ratio increases to 30%,the lifetime of the module decreases by 56.1%compared with that of the solder layer without voids.In addition,the closer the distance between the voids and the corners/sides,the more significant the decrease in the lifetime of the solder layer,with a maximum reduction of 6.2%.The influence of randomness of voids’distribution on the lifetime is about 3.1%.3.The correlation between the propagation of microcracks in solder and grain orientation was obtained through the bending experiments of pre-cracked solder micro-cantilever beams under different damage states.With the thermal cycling continues,the critical fracture J-integral value is significantly reduced,even with a slash more than 50%.Besides,the degradation of fracture toughness is related to the dislocation activity and the recrystallization process of the die-attach material during the thermomechanical fatigue.4.By simultaneously monitoring and comparing the degradation trend of the aging parameters at both terminals of the Kelvin source and common source of SiC MOSFET,it is found that the continuous increase in the conduction voltage(V_on/V_F)of the two monitoring terminals shows the degradation of the chip,while the stepped increase represents the failure of the bonding wires.In addition,the lifetime of power module in body diode mode is about 1.8 times that in saturation mode,and the degradation rate of V_F in this mode is suppressed,resulting in thermal resistances R_th,jf increasing by more than 14%.Under power cycle stress,the degradation at the chip level and packaging level competes with each other,which accelerates the occurrence of failure.5.The decoupling of the electro-thermal imbalance behavior is realized through thermal network model containing the thermal coupling effect and the electrothermal characteristics of branched chip.The results show that thermal coupling plays a leading role in the temperature imbalance of paralleled chips,while the imbalance of dissipated power,namely,the imbalance of steady-state current sharing,dominates the imbalance of temperature rise caused by self-heating.The steady-state current sharing errors predicted by decoupling the thermal coupling effect of thermal resistance network is within 5%.During the degradation process of packaging,the aggravation of electro-thermal imbalance can lead to large circulating current on the bonding wires of Kelvin source and the burning out.This thesis reveals the degradation mechanism of packaging structures and coupling failure mechanism of SiC MOSFET modules,including a series of reliability problems such as coupled damage mechanism,coupled chip-package failure and coupled electric-thermal imbalance,which provides data support and reference basis for the development of SiC MOSFET module packaging process and reliability collaborative design.