Design Of Directory-Protocol Based Cache Architecture

Chip multi-processors (CMP) are rapidly emerging as an important design paradigm for high performance computing. The structure of shared on-chip cache may trigger data inconsistent problems. The protocol of cache coherence should be introduced in CMP, which is similar to that in conventional multi-processors system. Directory Mechanism has more scalability than Snooping Coherence Mechanism, whilst it would lead to more overhead of directories and latency in memory directory access. Reducing the memory access latency and memory overhead of directories of directory-based protocol is one of critical problems for performance optimization of CMP systems.A Dynamic-Sharing-Relation directory protocol based cache architecture is proposed. Data sharing is an dynamic action among the simultaneously executing threads in CMP. Only a limited number of data is shared within a definite period of time on the basis of the temporal locality of program, which indicates that the number of records of sharing relation is limited. Compared with the design of reserving spaces for all data, the proposed protocol is only maintain directories of dynamic sharing data. The directory storage is designed as on-chip-implemented infrastructure, and data sharing state transformation is accomplished under MESI protocol.In order to simulate the performance of the system, four standard benchmark programs are designed on the SESC simulator to evaluate the effectiveness of the Dynamic-Sharing-Relation directory Protocol. The results show that the cache system reduces the memory overhead of directory protocols and improves system performance, and the associativity of directory storage has minimal impact, integrating more cores demands more capacity of directory storage.