Research And Implementation Of Process Trusted Detection Technology Based On DC-VDC Two-level TDC

With the globalization of the integrated circuit supply chain,in order to shorten the research cycle and reduce the cost of research and development,chip companies have separated design and manufacturing by commissioning third-party foundary.As a result,the possibility of malicious attacks on the chips has increased dramatically.In order to ensure the security of the chip production process,the technology of process trusted detection is studied in this thesis.The subject of this thesis is from the National Key Basic Research Program of China(973project).Aiming at the process trusted problem introduced by the third-party foundry manufacturing process,a detection structure based on DC-VDC two-level TDC is designed in this thesis.The detection structure has the characteristics of high precision and low overhead,which can be used for large-scale integrated circuits Process trusted testing.Based on the detection structure,a complete detection process is established.Firstly,a detection structure is implanted in the chip design stage,and then the detection structure is used to extract the path delay fluctuation range under the process deviation and the delay decay rate under the aging stress as the golden sample.Finally,the delay feature of chip to be tested are compared with the golden sample to estimate the trust of the chip production process.A malicious process engineer can slightly adjust some process parameters to reduce the performance and service life of the chip,and it is not easy to find.Therefore,in this thesis,the influence of uncontrolled process on the performance of the gate circuit is analyzed first.Analyze the process of gate and ion implantation that may be introduced into the process Trojan,extract process parameters that have a greater influence on the uncontrolled process.In the 55nm process,Hspice is used to analyze the effects of uncontrolled process on the delay and power consumption of the three-level inverter circuit at different process corners.The experimental results show that the uncontrolled gate process has a small effect on the initial performance of the gate circuit,which is almost submerged within the range of process deviation,but can accelerate the speed of gate circuit performance degradation.The uncontrolled ion implantation has a significant impact on the performance of the gate circuit and attack the local location of the chip.In addition,circuit performance is more sensitive to the uncontrolled process of NMOS devices and should be the focus of protection.In this thesis,the effect of the aging effect on the delay and power consumption performance of the gate circuit is analyzed,and it is proved that with the decline of the threshold voltage,compared with the power consumption,the delay variation is larger and the linearity is better.Therefore,the research direction of detecting process Trojan based on path delay side channel analysis is determined.Then,a detection structure based on DC-VDC two-level TDC is designed in this thesis.It combines the advantages of two types of TDC structure,delay chain and vernier delay chain,to achieve a wide range of high-precision time measurement.In order to reduce the influence of process deviation on time measurement accuracy,a linear regression-based calibration method suitable for the detection structure of this thesis is proposed.By processing the results of multiple time measurements,the impact of process deviation is distributed to each delay unit to obtain the average of the delay units.The relevant index parameters of the two-level TDC in this thesis are obtained through simulation tests:(1)the effective is 16.2ps;(2)the dynamic range is 2.109ns;(3)the area overhead is 558.32 um²;(4)the response time is1.23 ns;(5)the measurement error is within 15ps;(6)it has good linearity,and all parameters meet the delay detection requirements.Finally,the detection technology in this thesis was verified by software simulation and tape test.The RISC-V processor is used as the carrier circuit,and the short path is selected as the process-sensitive path to implant the detection structure.The 55nm process is used to complete the backend design and tape verification of the detection scheme.According to the hardware implementation results,the area overhead introduced by the detection scheme in this thesis is 1980.72um²,and the power consumption overhead is 0.5315uw,compared to the carrier circuit,which are both on the order of 10^-3.In this thesis,the process degradation of the chip is simulated by adjusting the delay decay factor during simulation and the PCB board test voltage during chip testing to verify the detection scheme's ability to detect process changes.The results show that the detection technology in this thesis can detect the delay change caused by the decline of different processes.By comparing with the normal delay data,it can effectively detect the process Trojans that exceed the process deviation and the recessive process Trojans that significantly accelerate the decline.