Hardware Trojan detection using multiple-parameter side-channel analysis

Malicious alterations of integrated circuits during fabrication in untrusted foundries pose major concern in terms of their reliable and trusted field operation. It is extremely difficult to discover such hardware "Trojan" instances using conventional structural or functional testing strategies. In this thesis, we propose a novel non-invasive, multiple-parameter side-channel analysis based Trojan detection approach that is capable of detecting malicious hardware modifications in the presence of large process variation induced noise. We exploit the intrinsic relationship between dynamic current ( IDDT) and maximum operating frequency (F max) of a circuit to distinguish the effect of a Trojan from process variation induced fluctuations in IDDT. We propose a vector generation approach that can improve Trojan detection sensitivity. We show that along with IDDT and Fmax, one can also use quiescent current ( IDDQ) as a third parameter to increase the confidence level during the decision making process. Simulation results with two large circuits, a 32-bit integer execution unit (IEU) and a 128-bit Advanced Encryption System (AES) cipher, show a detection resolution of 0:04% can be achieved amidst +/-20% parameter (Vth) variations. The approach is also validated with experimental results using 120nm FPGA (Xilinx Virtex-II) chips. The measurement results for the IEU core show that sequential Trojans of varying size can be reliably detected by eliminating process noise.