Design And Implementation Of Data Transfer Controller And Hardware Trojan Research In Secure Trusted SoC

The secure trusted SoC is playing an increasingly important role in many areas.At present,in terms of hardware research in the field of information security,safe and reliable SoCs that are completely independently developed in China are still lacking.Thus,designing a system-level real-time encryption and decryption SoC chip that supports multiple encryption and decryption algorithms and supports multiple interfaces is completely necessary.The research content of this dissertation includes the design of a secure trusted SoC chip architecture with completely independent intellectual property rights,the controller design for acceleration and decryption data flow,and the hardware Trojan horse research based on the SoC chip.Firstly,the secure and trusted SoC chip is implemented using the AMBA architecture.In order to improve the transmission efficiency of the encryption and decryption data stream inside the chip,the design of the encryption and decryption data flow controller is introduced in the chip architecture.After the introduction,the transmission efficiency of encryption and decryption was up to 233%.In addition,this structure frees CPU resources and occupation of the bus and improves the processing power of the entire chip.In addition,the design of the QSPI pass-through path in this module provides a solution for the start-up of the upper processer Zynq FPGA.Secondly,a hardware-software co-verification environment based on the Xilinx XC7K325 and Xilinx Zynq XC7Z030 was built.The software configuration of the CPU C*Core CS322 d is programmed via CodeWarrior software.The encryption and decryption data flow controller passed the functional verification in the SoC architecture and passed all the rules of FPGA verification on the hardware and software co-imitation platform.The SoC will be taped out at 2018.06 under the GSMC 0.13?m CMOS process.Due to the use of third-party IP cores and the participation of foundries,malicious circuits may be implanted in the chip life cycle.The security of the encryption and decryption data flow controller in the security SoC is very important.It is very important to detect and protect the hardware Trojan horse.Therefore,in this paper,the UART interface and the SM4 algorithm are used to design and implement the interface Trojan and key leakage Trojan.Through the design and research of Trojans,Trojan detection and prevention experience has been accumulated.The structure of the counter-type Trojan trigger circuit has been improved,resulting in a 25% reduction in dynamic power consumption.The Trojan was implanted in the UART interface for FPGA implementation,successfully tampered with the UART interface data.And thus proposed the detection idea of the Trojan probe.The design of an ultra-light key leaking Trojan horse based on SM4 and the implementation of an FPGA were performed.Only 4 exclusive OR gates were used in the Trojan payload section to successfully implement key leakage.It is estimated that power consumption and area consumption are less than 1% of the usual solution.Trojan horse protection experience has been accumulated.During the Trojan horse detection process,it is not only necessary to pay attention to whether there is a direct disclosure of the key,but also whether there is output of redundant information such as wrong ciphertext.Once the two types of Trojans triggered,it will make the SoC interface data tampered,and indirect key leakage.The hardware Trojan design of this article provides experience and lays a solid foundation for the hardware Trojan detection and defense research.