Removal Of Mura Defect In Large Size TFT-LCD Panel And Implementation On FPGA

TFT-LCD panel makers is now facing a big challenge that named Mura defects problem,its form mainly on the front panel in different luminance images show especially low light images produced by uneven spots,blemishes,low contrast,blurred edges,these defects with irregular shape,it will affect the quality of TFT-LCD screen display,if you can’t control the occurrence of these defects will lead to the low yield of product to the factory,will seriously affect the production of panels,increase the cost of production.After studying all kinds of image interpolation algorithm,this paper analyzes the advantages and disadvantages of various algorithms,based on this,according to the characteristics of the Mura defect,the design of large size TFT-LCD panel Mura defect removal of hardware module,can not only realize gray-scale compensation,also can realize chrominance compensation,and achieve the complete design on FPGA,and verify the defect removal effect of the module.Mura defects is to remove the core image interpolation algorithm,after several traditional interpolation algorithms are studied in this paper,compares the different LUT algorithms of chrominance compensation data interpolation effect,unknown information on comprehensive quality after interpolation and the consumption of resources,using the bilinear interpolation and linear interpolation method and the correction module implements the TFT-LCD panel Mura defect removal.In the FPGA design,introduces in detail the relationship between the function of each module,this paper proposes a hardware algorithm process,and the bilinear interpolation algorithm in more multiplication is optimized,the algorithm of optimized resource consumption,less and reduce the area of the circuit,improve the operation speed and efficiency of the whole module.Using SRAM as the line buffer and using the ping-pong operation method,the data flow can be pipelined,so that when the pipeline is full,each clock can calculate an interpolation result.Each module designed in this paper uses the Verilog HDL for RTL code design and Synopsys VCS simulation software for functional simulation.The results show that the module designed in this paper can completely remove the Mura defect of the large size and high resolution TFTLCD panel,and the uneven brightness defect displayed on the screen can be compensated to make the brightness even,without significant brightness difference on the whole screen.Finally,the designed modules were integrated on the SOC/ASIC verification platform of S2 C Single KU115 Prodigy Logic Module based on Xilinx’s Kintex Ultrascale KU115 FPGA chip.The integrated results showed that a total of 17943 registers,46829 LUTs,31 BRAM and 36 multiplicators were used.The maximum working frequency of the module in this design is 148.5MHz,which can remove real-time defects of 4K and 8K resolution video and image displayed on large-size LCD display or screen.