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High Energy Efficient 4H-SiC MESFET Design With Partially Low Doped Channel

Posted on:2021-08-28Degree:MasterType:Thesis
Country:ChinaCandidate:Y B TongFull Text:PDF
GTID:2518306050469824Subject:Master of Engineering
Abstract/Summary:
With the development of microwave power devices,4H-SiC MESFET devices have attracted attention due to their excellent characteristics in high power,high frequency,and high temperature and high pressure resistance.Today,microwave power devices have more and more output power,and their energy conversion efficiency has become a new hotspot in microwave power device research.Microwave power devices with high energy efficiency can not only save energy and protect the environment,but also reduce the heating of the device.Therefore,it is the main research goal of this paper to ensure that 4H-SiC MESFET devices have good output power and improve their power added efficiency.First,ADS is uesd to simulate the principle of device high energy efficiency in this paper.The effects of device transconductance,threshold voltage,gate-source capacitance,and saturation drain current on PAE were analyzed by the control variable method.Under the same operating conditions,the smaller the threshold voltage(absolute value)and the gate-source capacitance are,the larger the PAE of the device is.The larger the transconductance and saturation leakage current are,the larger the PAE of the device is.In addition,this paper proposes a method to verify the reasonableness of the device model in ADS by comparing the I-V characteristic curve.By comparing the I-V characteristic curve obtained from ISE-TCAD and ADS,we can determine whether the model is reasonable.A novel high energy-efficient 4H-SiC MESFET device structure with a partially low doped channel under the gate is proposed in this paper for the first time.The channel electric field of the device and the depletion layer region under the gate are modified by the partially low doped channel,so that the device has a higher output power density and higher PAE.Compared with DR-MESFET,simulation results show that the PLDC-MESFET has improved in various aspects.The new structure has a maximum output power density of 5.928 W / mm,a cut-off frequency of 16.9 GHz,and a power added efficiency of 46.17%,which are 6.7%,6.3%,and 16.7% higher than the original device,respectively.The proposed PLDC-MESFET is optimized to obtain a higher PAE.By optimizing the thickness and doping concentration of the low-doped region under the gate of the PLDC-MESFET,the channel electric field distribution and the depletion layer under the gate can be more reasonable,thereby improving the PAE of the device.Simulation results show that the device has the best PAE under the conditions that the thickness of the PLDC is 0.15 μm and the concentration of the PLDC is 1 × 1015 cm-3.At this time,the maximum output power density of the optimized device is 4.56 W / mm,which is 17.9% lower than that of the original device.Its cut-off frequency is 15.95 GHz,which is basically the same as that of the original device.Its power added efficiency is 51.90%.Compared with the original device,the PAE of the PLDC-MESFET is improved by 31.19%.Therefore,the optimized device is sacrificing part of the DC performance and obtaining higher power added efficiency by balancing the various parameters of the device.For the first time,the impact of device operating conditions on PAE is presented in this paper.By changing the operating conditions of the device,the influence of gate voltage and input signal power on the PAE of the device is analyzed.Simulation results show that the PAE of the device will change under different gate voltages,but the optimized PLDC-MESFET has a higher PAE than the original device,and the output power of the two devices is basically the same.Compared to the original device,PLDC-MESFTE has the highest power added efficiency improvement when the gate voltage is-8V in the entire simulation range,and its value is 86.38%.When the gate voltage is-6V,the optimized device has the highest power added efficiency and the value is 56.27%.The increase of input signal power will increase the power added efficiency and output power of the device.In the entire simulation range,the optimized PLDC-MESFET has a higher PAE than the original device,and the output power of the two is basically the same.
Keywords/Search Tags:4H-SiC MESFEET, Power Added Efficiency, Partially Low Doped under the Gate, Output Power
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