Design Of Novel S Band Semiconductor Power Devices With High Efficiency

As the technology of wide bandgap semiconductor materials and devices continues to mature,its advantages in materials and devices have become increasingly apparent,and practical applications have been achieved in fields such as power electronics and lighting engineering.With the rapid development of modern wireless communication technology,the requirements for the performance indicators of RF power amplifiers are getting higher and higher,and "high energy efficiency and high performance at the same time" has become the main development trend now and after.A novel 4H-Si C MESFET(MRB 4H-Si C MESFET)structure with multiple recessed buffer layers is proposed for the first time in this paper.Compared with the double recessed buffer layer(DRB 4H-Si C MESFET)structure,MRB 4H-Si C MESFET structure improves the output power density and cutoff frequency of the device at the same time.The problem of mutual restriction between the DC performance and AC performance of the device is solved.The structure applies the principle of superjunction.By reducing the channel thickness between the source and the drain,the channel is further depleted and the resistance of the channel region is increased,so that the electric field intensity distribution in the drift region is more uniform and the breakdown voltage is higher.The output power density has been improved and the device has achieved excellent DC characteristics.The nonrecessed region near the source side functions as an auxiliary gate depletion and suppresses the extension of the depletion layer to the source side under the gate.By this the gate-source capacitance of the device is improved while maintaining a slight decrease in the transconductance.Thereby the cut-off frequency of the device improved and allows the device to maintain good AC characteristics.The ISE-TCAD simulated results show that the breakdown voltage of DRB 4H-Si C MESFET is 61.50 V,and MRB 4H-Si C MESFET is 97.10 V,which is 57.89% higher than the former.The saturated drain current of DRB 4H-Si C MESFET and MRB 4H-Si C MESFET are 376.30 m A/mm and 397.50 m A/mm,respectively.And the latter increased by 5.63% compared with the former.Through further calculations,the maximum output power density of the MRB 4H-Si C MESFET structure is increased by 87.10% compared to the DRB 4H-Si C MESFET.The gate-source capacitance was reduced from 0.606 p F/mm for the DRB 4H-Si C MESFET to 0.580 p F/mm for the MRB 4H-Si C MESFET,a reduction of 4.29%.The transconductance of the MRB structure and the DRB structure are 66.72 m S/mm and 68.38 m S/mm,respectively.The transconductance of the MRB structure is slightly reduced.The cut-off frequencies of the DRB 4H-Si C MESFET and MRB 4H-Si C MESFET are 16.89 GHz and 17.41 GHz,respectively,and the cut-off frequency of the MRB structure is increased by 3.10%.In combination with all of the above simulation results,MRB 4H-Si C MESFET have more superior DC and AC characteristics compared to DRB 4H-Si C MESFET.In addition,the P-buffer layer depression length and depth in MRB 4H-Si C MESFET were optimized.The DC output characteristics and AC characteristics of the device achieved the best when the length of the unrecessed buffer layer is 0.10?m on the source side and 0.20?m on the drain side,the depth of the recessed buffer layer is 0.15?m.The power-added efficiency of the device at this time is 38.18%.The relative significance and influence of each parameter of the 4H-Si C MESFET device in the model is simulated and analyzed by using ADS circuit simulation software and the Load-pull circuit in this paper.And some key parameters that are relatively sensitive to the power-added efficiency(PAE)and their influence directions are analyzed.In order to reduce the energy consumption of the device,in response to the call for high energy-efficient targets,the recessed length and depth of the MRB 4H-Si C MESFET structure are further optimized based on the power-added efficiency of the device.The value of the optimized structure parameters is obtained.Including the length of the unrecessed buffer layer at the source side is 0.50?m,the length of the unrecessed buffer layer at the drain side is 0.00?m,and the recessed depth is 0.15?m.At this point,the power efficiency of the device reaches an optimal value of 53.56%.