Research On Design Of True Random Number Generator Based On Probability Circuit

Random sequences generated by True Random Number Generator (TRNG) are widely used in the application of security such as key generation of cipher algorithm or electronic signature certification, they are the key part to ensure the security of information system. With reducing of the feature size of IC and a higher integration of SoC chips according to Moore’s Law, we need a smaller size of TRNG that is suitable to integrate into SoC chips. At the same time, the power of TRNG need to be smaller to satisfy the tendency of low Carbon and energy consumption of IC design. At present, there is not a TRNG design method that can both meet low-power consumption and small design area.In this thesis, we use probability circuit units to design TRNG, using the iteration of probability distribution current signal to generate output of random oscillating. Probability circuit units work in the sub-threshold area which has a small working current, this makes the design power very small. Besides, as probability circuit units have a simple structure which constructed only by MOS-FETs without any passive components, the design area of this method is small. We design probability circuit units so called soft inverter and soft XOR-gate according the logic function of digital inverter and XOR-gate to implement Fibonacci feedback oscillating structure. Meanwhile, for the special iterative characteristic of soft XOR-gate, we design probability signal amplifier connected after every soft XOR-gate to disturb the probability distribution signal far away from the stable point and avoid probability distribution signal from stopping oscillating after iteratively getting through soft XOR-gates. Besides, we primarily analyze the security of the TRNG at both sides of generation algorithm and structure of circuit implementation, so the randomness of output random sequence can be estimated in advance before we deal with the design implementation practically.This design is implemented in the process of SMIC0.13um and simulated using Virtuoso Spectre provided by Cadence Ltd. The randomness of output random sequence is pretty good after statistic distribution test. Comparing to the past TRNG design, this design has outstanding advantages in both power consumption and area.