| This thesis report details the design process of a hardware random number generator in a 0.12mum CMOS process. The random number generator uses the amplified RTS (Random Telegraph Signal) noise of minimal MOS devices as the source. The noise is amplified and then converted into digital voltage levels (random numbers) by means of a comparator. A fully differential approach has been developed for the design of the random number generator which serves many advantages such as high common-mode rejection ratio, power supply rejection ratio etc. First the design specifications of the system have been identified, based on the requirements of the RNG (Random Number Generator), which also includes the immunity of the circuit against the circuit coupled noise. Then the individual components of the RNG have been designed to meet the required goals defined by the specification. Finally the system and its performance have been simulated both pre and post-layout. |
