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Algorithms And Hardware Implementation For Decoders Of Turbo Product Codes

Posted on:2020-06-26Degree:MasterType:Thesis
Country:ChinaCandidate:Y Q WangFull Text:PDF
GTID:2518305735451774Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
Turbo product codes(TPCs)are one of the important error correcting codes which can achieve the Shannon limit with a reasonable decoding complexity.A TPC codeword is constructed by multiple dimensions of block codes that are referred to as component codes.The component codes in the same dimension can be encoded and decoded at the same time.Such a highly parallel structure makes TPCs very suitable for applications which need high throughput.Moreover,the minimum code distance of TPCs is large.So TPCs have low error floors.These advantages make TPCs have attracted broad attention since they are invented.TPCs have been included in many standards such as IEEE 802.16.TPCs are also considered suitable for 100G optical communication and storage.TPCs can be constructed by many kinds of block codes,such as BCH codes,polar codes,and LDPC codes.The most popular codes used to construct TPCs are BCH.The decoding algorithms for TPCs based on BCH codes are the Chase algorithm and ordered statistics decoding(OSD)algorithm and so on.The Chase algorithm provides a good tradeoff between error-correcting performance and decoding complexity.TPCs based on other block codes other than BCH codes have also attract some attention of scholars.Most of TPC decoders in open literature are based on the Chase algorithm.A troublesome problem of TPC decoders is the two-dimension memory access confliction.Many methods of this problems have been proposed.These methods make the hardware implementation of TPC decoders with high throughput possible.The Chase-2 algorithm gives a good tradeoff between complexity and performance.However,the decoding complexity of the Chase algorithm is still high.Reducing computational complexity is worth studying.The throughputs of most decoders in open literature are around 10Gbps or less than 10Gbps.These decoders cannot meet the demands of 100G optical communications.Viasat Inc has give the synthesis results of the TPCs decoders for 100G optical networks.However,the details of the decoder were not given.The area consumption and power of TPC decoders with 100Gbps throughput are very large.So it is important to reduce the complexity of TPC decoders.In this paper,the encoding algorithms and decoding algorithms of TPCs are recalled.The curves of bit error rates(BERs)of different decoding algorithms and different TPCs are given.The TPCs based on polar codes are studied.The curves of BERs of TPCs based on polar codes are also given.To reduce the decoding complexity of the Chase-2 decoding algorithm,two modified algorithms based on the Chase-2 algorithm are proposed.The first algorithm does not use the extrinsic information.It is a soft-input hard-output algorithm.In the conventional Chase-2 algorithm,the extrinsic information is generated and used to update the soft inputs.The complexity of generating extrinsic information is very high.Moreover,updating the extrinsic information stored in memory incurs the two-dimension memory access confliction.The proposed soft-input hard-output decoding algorithm does not generate the extrinsic information.So the decoding complexity is reduced a lot.The second algorithm simplifies the method of generating the extrinsic information.In this algorithm,the absolution values of soft inputs for a component codes are the same.Only one subtraction operation is needed when generating the extrinsic information.The complexity of generating the extrinsic information is reduced greatly.This algorithm incurs negligible performance loss.In this paper,a 100-Gbps TPC decoder which is suitable for optical communications is proposed.This decoder is synthesized using TSMC 28nm technology.The synthesis results show that area efficiency of the proposed decoder is nearly 2 times larger than that of the work of art.Moreover,a decoding architecture using simplified method of generating the extrinsic information is proposed.The synthesis results under 90nm technology show that the simplified method of generating the extrinsic information saves 40%of the area.
Keywords/Search Tags:VLSI, error correcting code, turbo product code
PDF Full Text Request
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