Hardware Implementation Of Stack AutoEncoder Algorithm Based On Systolic Array Architecture

As a frontier interdisciplinary subject,Artificial Intelligence has been formed and developed for decades.Machine learning,as one of the most important branches of AI,has been paid more and more attention and developed by academia and industry.Deep learning is an important part of machine learning,which plays an increasingly significant role in pattern recognition,image compression,information retrieval and other fields.As the key algorithm,deep neural network is becoming more and more complex,and computing power has become an important factor restricting the development of artificial intelligence.Using reconfigurable computing to accelerate the hardware can support a variety of neural networks to complete training and inferring operations,which has become one of the important ways to solve the problem of insufficient computing power.This paper focuses on a Stacked Auto Encoder(SAE)algorithm based on self-encoder in neural network,including the inferring and training process of the algorithm,and expounds the advantages of the algorithm and application scenarios.Combining with reconfigurable computing and stack autoencoder algorithm,this paper accomplishes the following three tasks:Firstly,two design schemes of SIMD architecture and systolic-like array architecture model of S AE algorithm are explored,and periodic accurate system model simulation is established by SystemC language.By comparing the simulation results of two different architectures,it is concluded that under the condition of single sample or simultaneous inferring of multiple samples,the acceleration effect of systolic-like array architecture is significantly better than that of SIMD architecture.Secondly,a reconfigurable systolic-like array with 1024 machine learning units(MLUs)can be reconstructed in each processing unit.Five computing modes can be reconstructed,including counting,addition,multiplication,multiply-accumulate and accumulation,which can support some artificial intelligence algorithms such as Convolutional Neural Networks(CNN),Short-Term Memory(LSTM),and SAE.Thirdly,the hardware implementation of S AE algorithm is accomplished by using systolic-like array architecture.The data storage module,control module,address generation module,data partition module and storage control module are designed and completed.On the basis of systolic-like array as hardware architecture,pipeline operation of arithmetic inferring,multi-channel parallel computation of single sample and synchronous computation of multiple samples can be realized simultaneously.In addition,some computational time and memory access time can be masked by pingpong operation.The correctness of hardware implementation is verified based on UltraScale XCVU440 FPGA of Xillinx Company.Comparing with the calculation results in reference[56],the speed of inferring in this paper is at least three times faster than that in the case of less resource consumption.In addition,the SAE hardware implementation scheme proposed in this paper also has good scalability and tailorability,and has a good reference value and guiding significance for the hardware implementation of the same type of algorithms.