Design And Implementation Of High-speed Data Acquisition And Editing Device

With the rapid development of high-speed data acquisition and editing device,as an important part of data transmission in flight test,it plays a vital role in sampling aircraft state parameters and external environment information.Relying on the "design and implementation of high-speed data acquisition,editing and recording device",the high-speed data acquisition and editing device is designed to realize the acquisition,framing and transmission of various data in flight test.These test data provide theoretical basis and technical support for the design,verification and improvement of aircraft.The aircraft avoids the possible accidental risk.Firstly,according to the principle of modularization,the high-speed data acquisition and editing device is divided into main control module and power module.Main control module is designed to realize the function of data transmission.Power module is designed to realize the function of power supply.Secondly,this paper takes the hardware circuit as the starting point.The power supply circuit is designed according to the requirements of power on timing.In order to realize the storage of FPGA program,the flash configuration circuit is designed.In order to receive two channels of image data with burst rate up to 2.5Gbps,SRIO interface circuit is designed.In order to solve the problem of too fast SRIO burst transmission rate,DDR3 SDRAM cache array is designed,and various topology types are compared.Finally,Fly-by topology is selected to improve signal integrity;Considering the practical application scenario of the acquisition and editing device,a transformer coupled 1553 B interface circuit is designed to realize the real-time monitoring and receiving of bus data.In order to transmit the data received by the high-speed acquisition and editing device to the memory,the LVDS interface circuit is designed.At the same time,in order to improve the reliability of data transmission,the possible noise sources are analyzed and processed accordingly.In the logic design,the SRIO interface logic based on HELLO format data packet through SWRITE operation is designed to transmit data.The control of DDR3 SDRAM read and write operation is realized through MIG IP core.The mode configuration and dual buffer structure of 1553 B are designed,and the protocol chip address line is multiplexed to improve the efficiency of data transmission.In order to improve the convenience of later maintenance of the high-speed acquisition and editing device,the online updating of FPGA program is also designed.Finally,a test platform is built to test the function of the high-speed acquisition and editing device.The test results show that the high-speed data acquisition and editing device can effectively collect data and complete framing to meet the task requirements.However,in the process of device debugging,the program upgrade will fail due to power cut-out.Aiming at this problem,Fallbcak mode is designed to improve program updating.